IEEE 2015 VLSI DESIGN AND ANALYSIS OF APPROXIMATE.pptx

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DESIGN AND ANALYSIS OF APPROXIMATECOMPRESSORS
FOR MULTIPLICATION
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ABSTRACT

• Inexact (or approximate) computing is an
  attractive paradigm for digital processing at
  nanometric scales. Inexact computingis
  particularly interesting for computer arithmetic
  designs. This paper deals with the analysis and
  design of two new approximate 4-2compressors for
  utilization in a multiplier. These designs rely
  on different features of compression, such that
  imprecision in computation(as measured by the
  error rate and the so-called normalized error
  distance) can meet with respect to circuit-based
  ?gures of merit of adesign

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• (number of transistors, delay and power
  consumption). Four different schemes for
  utilizing the proposed approximate compressors
  are proposed and analyzed for a Dadda multiplier.
  Extensive simulation results are provided and an
  application of the approximate multipliers to
  image processing is presented. The results show
  that the proposed designs accomplish signi?can
  treductions in power dissipation, delay and
  transistor count compared to an exact design.

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EXISTING METHODS

• 1. Truncated multiplication method
• 2. An imprecise array multiplieris used for
  neural network applications omit some ofthe least
  signi?cant bits in the partial products and
  thusremoving some adders in the array.
• 3. A variable correctiontruncated multiplier
  changes the correction term based on column n - k
  - 1. If allpartial products in column n - k - 1
  are one, then the correctionterm is increased.
  Similarly, if all partial products in thiscolumn
  are zero, the correction term is decreased.
• 4. 4-2 exact compressors for approximate
  multiplication

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PROPOSED METHOD

• Two novel approximate 4-2 compressorsare proposed
  and analyzed. It is shown that thesesimpli?ed
  compressors have better delay and power
  consumptionthan the optimized (exact) 4-2
  compressor designs. These approximate
  compressorsare then used in the restoration
  module of a Dadda multiplier. The multiplier is
  designed using these proposed compressors. A
  (exact) multiplieris usually composed of three
  parts (or modules) .

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• Partial product generation.
• A carry save adder (CSA) tree to reduce the
  partial products matrix to an addition of only
  twooperands.
• A carry propagation adder (CPA) for the ?nal
  computationof the binary result.
• In the design of a multiplier, the second module
  playsa pivotal role in terms of delay, power
  consumption andcircuit complexity. Compressors
  have been widely usedto speed up the CSA tree and
  decrease its powerdissipation, so to achieve fast
  and low-power operation.The use of approximate
  compressors in the CSA tree of amultiplier
  results in an approximate multiplier.

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ADVANTAGES

• The approximate compressors reduce the
  transistor, power consumptionand delay compared
  with an exact design.