IEEE 2015 VLSI IMPLEMENTATION OF SUBTHRESHOLD ADIABATIC LOGIC FOR ULTRALOW-POWER APPLICATION.pptx

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IMPLEMENTATION OF SUBTHRESHOLD ADIABATIC LOGIC
FOR ULTRALOW-POWER APPLICATION
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ABSTRACT

• Behavior of adiabatic logic circuits in
  weakinversion or subthreshold regime is analyzed
  in depth for the ?rsttime in the literature to
  make great improvement in ultra-lowpowercircuit
  design. This novel approach is ef?cacious
  inlow-speed operations where power consumption
  and longevityare the pivotal concerns instead of
  performance. The schematicand layout of a 4-bit
  carry look ahead adder (CLA) has beenimplemented
  to show the workability of the proposed logic.

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• The effect of temperature and process parameter
  variations on subthres hold adiabatic logic-based
  4-bit CLA has alsobeen addressed separately.
  Postlayout simulations show thatsubthreshold
  adiabatic units can save signi?cant energy
  comparedwith a logically equivalent static CMOS
  implementation.

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EXISTING METHOD

• Adiabatic logic which increases the leakage
  current

PROPOSED METHOD
In general, the design of SAL requires a
deepknowledge of the main features of the adopted
logicstyle, such as power dissipation, leakage
current, impactof temperature variation,
operating frequency, and noiseimmunity. In this
paper, the behaviors of adiabaticlogic in
subthreshold regime are discussed in depth.To
demonstrate the workability of the adiabatic
logic circuitsin subthreshold regime, a 4-bit
carry look ahead adder (CLA)unit is adopted as a
reference circuit.
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ADVANTAGES

• Reduces the power consumption