ARM Architecture and Pipeline Organization

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ARM Architecture and Pipeline Organization
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• ARM7
• ARM7 is a group of older 32-bit ARM processor
  cores
• licensed by ARM Holdings

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ARM Architecture
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ARM Architecture (Cont)

• Enhancements in the ARM7 architecture
• Each instruction controls the ALU and shifter
• Auto-increment and auto-decrement addressing
  modes
• Multiple Load/Store
• Conditional execution

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ARM Architecture (Cont)

• Results
• High performance
• Low code size
• Low power consumption
• Low silicon area

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Pipeline Organization

• Increases speed because most instructions are
  executed in single cycle.
• Versions
• 3-stage (ARM7TDMI and earlier)
• 5-stage (ARMS, ARM9TDMI)
• 6-stage (ARM10TDMI)

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Pipeline Organization (Cont)

• 3-stage pipeline Fetch Decode - Execute
• Three-cycle latency, one instruction per cycle
  throughput

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Pipeline Organization (Cont)
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Pipeline Organization (Cont)

• 6-stage (ARM10TDMI) of ARM7 comprises of
  following stages
• Fetch
• Issue
• Decode
• Execute
• Memory
• Write

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Pipeline Organization (Cont)
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