QUARTIC Frontend Electronics

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QUARTIC Frontend Electronics

• Lars Holm, Jim Pinfold,
  Jan Schaapman the QUARTIC Group

• Associated Group (GASTOF)
• University of Louvain Krzysztof Piotrzkowski

René Magritte Empire of Light
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Frontend Electronics Development

• The frontend electronics work will proceed in
  three phases
• Phase 1 Planned for next test beam starting
  March 7th it includes
• An amplifier (Hamamatsu, Ortec, Phillips)
• An ORTEC CFD
• A Phillips TDC (7186)
• Phase 2 The amplifier and CFD will be replaced
  by custom electronics
• Phase 3 The commercial TDC will be replaced by
  a custom board based on the CERN HPTDC
  http//micdigital.web.cern.ch/micdigital/hptdc/)
• The aim is 10ps resolution overall - this could
  be achieved by 30 ps time resolution per Quartic
  element measurement (assuming we are not affected
  by coherent noise)

James L Pinfold
Manchester 2006
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Phase 1

• The ORTEC 934 Quad Constant-Fraction 100- MHz
  Discriminator is a single-width NIM module with 4
  channels. Time resolution 50ps
• The Phillips TDC has
• 16 channels
• 12 bit dynamic range
• Resolution down to 25 psec/count

James L Pinfold
Manchester 2006
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Phase 2 (1)

• New boards from Alberta and Louvain
• The Alberta board contains both the amplifier and
  the CFD
• We are aiming at 20 ps?30ps resolution with the
  CFD
• Each board has 4 channels
• The first prototype should be available at the
  end of Feb. 07

James L Pinfold
Manchester 2006
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Phase 2 (2)
O U T P U T T O H P T D C
input
CFD
Shaping
Phillips BGA2717 wideband amp Chips are used
used in the input configuration of the CFD.
2 Analog Devices ADCMP582 comparators (10ps
jitter) are used, one for the threshold
acceptance and the 2nd sensing the CFD zero
xing
James L Pinfold
Manchester 2006
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Phase 3 (1)

• Move to the HPTDC based solution
• Our approach to the TDC implementation is based
  on the ALICE ToF boards (NIMA 533 (2004)
  178182)
• We have 3 board types one for AMP-CFD and two
  for the TDC (a master board and slave boards)
  to reduce noise

James L Pinfold
Manchester 2006
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Phase 3 (2)

• Some information on the CERN HP-TDC chip
• 32 ? channels/chip? Size2.72.7 cm2 ?
• External clock40MHz?Synchronized to bunches.
• Internal clock 40MHz / 160 MHz / 320 MHz
  internal
• Time resolution Typical values 0.72 bin RMS (17
  ps) very high resolution mode
• To get high resolution we need to gang 4 channels
  thus a 32 channel chip goes to a 8 channel chip
• Variation with temperature Maximum 100ps change
  with 10 Deg. change of IC temperature.
• Cross talk Maximum 100 ps
• Dynamic range
• 22 bit very high resolution mode.
• Double pulse resolution Typical 5 ns. Guaranteed
  10ns

James L Pinfold
Manchester 2006
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Phase 3 (3)
ALICE Prototype ToF Card

• Initial idea is to have a small VME slave card
  using 4 HPTDC chips each with 32 channels and
  containing a FPGA
• The master card is based on its ALICE
  counterpart. At present the ALICE card contains
  an on board clock a FPGA, DSP, 2FIFOs Flash
  memory
• Lab bench tests and test beam results show that
  a 20 ps resolution has been achieved.

James L Pinfold
Manchester 2006
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Radiation Testing

• The electronics will be mounted in an area with
  moderately high radiation levels 15? 100
  Gry/year
• The HPTDC chip has been reported to be radiation
  tolerant to the 30 krad total dose level (300
  Gry) (http//www.nikhef.nl/toms/lhcb/otfe/lhcb-20
  01-13.pdf)
• At present it seems wise to design rad hard
  electronics for the FP420 region, rather than
  rely on shielding
• Obviously a program of radiation testing will be
  required

James L Pinfold
Manchester 2006
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