332:578 Deep Submicron VLSI Design Lecture 7 Crosstalk

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332578 Deep SubmicronVLSI DesignLecture 7
Crosstalk

• David Harris and Mike Bushnell
• Harvey Mudd College and Rutgers University
• Spring 2005

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Outline

• Fringing Field Capacitance
• Crosstalk
• Crosstalk Delay
• Crosstalk Noise
• Inductance
• Summary

Material from CMOS VLSI Design By Neil E. Weste
and David Harris
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Fringing Field Capacitance

• Simple adjustment Double ordinary calculated C
  to get fringing field C not accurate enough

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Crosstalk

• A capacitor does not like to change its voltage
  instantaneously.
• A wire has high capacitance to its neighbor.
• When the neighbor switches from 1-gt 0 or 0-gt1,
  the wire tends to switch too
• Called capacitive coupling or crosstalk
• Crosstalk effects
• Noise on non-switching wires
• Increased delay on switching wires

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Miller Effect

• Unimportant for short wires
• Very important for long wires
• Focus on charge delivered to wire B through Cadj
  coupling it to wire A
• Q CadjDV
• Miller Coupling Factor (MCF) shows how Cadj is
  multiplied to find effective capacitance
• Can use MCF 1.5 at logic level (before layout
  information available)

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Crosstalk Delay

• Assume layers above and below on average are
  quiet
• Second terminal of capacitor can be ignored
• Model as Cgnd Ctop Cbot
• Effective Cadj depends on behavior of neighbors
• Miller effect

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Crosstalk Delay

• Assume layers above and below on average are
  quiet
• Second terminal of capacitor can be ignored
• Model as Cgnd Ctop Cbot
• Effective Cadj depends on behavior of neighbors
• Miller effect

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Crosstalk Noise

• Crosstalk causes noise on non-switching wires
• If victim is floating
• Model as capacitive voltage divider

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Driven Victims

• Usually victim is driven by a gate that fights
  noise
• Noise depends on relative resistances
• Victim driver is in linear region, agg. in
  saturation
• If sizes are same, Raggressor 2-4 x Rvictim

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Coupling Waveforms

• Simulated coupling for Cadj Cvictim

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New VLSI Component -- Inductor

• Appeared because l shrank, f 4 GHz
• Chip bond wire inductance is a problem
• On-chip wire inductance now a problem
• Signal-carrying wire runs next to noisy VDD/VSS
  supply wire noise couples inductively -- Causes
  logic errors
• Background interconnect inductance is now a
  problem
• Inductance of cylindrical wire above ground
  plane
• L m ln 4h (use for wire bonds
  package pins)
• 2p d
• m wire magnetic permeability ( 1.257 X 10-8
  H/cm)
• h height above ground plane
• d wire diameter

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Inductor Behavior

• Current flows in loops
• Return path is power/ground network
• Power supply is an AC ground at f of interest
• Bypass C forms a low-impedance path between VDD
  and Ground
• Current flowing in loop generates a changing
  magnetic field
• Induces a voltage
• Changing magnetic fields produce currents in
  other loops
• Signals can couple inductively inductive
  crosstalk

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Inductance of On-Chip Wire

• w conductor width
• h height above substrate
• l wire length
• Package inductance values supplied by
  manufacturer
• Get an inductive voltage spike on a bond wire
  when you draw a large current in a short time
• dV L dI
• dt
• For high-speed chips, keep inductance down so
  that we dont disturb VDD
• MUST ACCOUNT FOR THIS AT 200 MHz OR HIGHER

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Inductance Example

• For an on-chip wire, h 1000 mm (1 mm thick
  chip)
• L 1.257 X 10-8 ln 8 X 1000 1
• 2p 1
  4000
• 1.8 x 10-9 H/mm
• Defeat L by
• Reducing height above ground plane of wire bond
  (use top metal layer as ground plane)
• Increasing wire diameter

(
)
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Physics

• L and C set speed of light in a medium
• Speed of light flight-time along wire of length l
• Signal velocity when current return paths same as
  conductors on which E field lines terminate

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Physics (continued)

• Signals travel at about ½ c
• If signal has E terminating on nearby neighbors,
  but currents returning in distant power supplies,
  v decreases
• Current flows along path of lowest impedance
• L minimized if current flows only near surface of
  conductor closest to return path

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Skin Effect

• Reduces effective cross-sectional area of thick
  conductors
• Raises effective R at high frequency
• Skin depth
• Important w is highest one with significant power
  in Fourier transform associated with faster
  signal edges

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Inductance Extraction

• 3-dimensional problem time consuming
• Depends on entire loop cannot be decomposed the
  way C extraction can be
• Use FastHenry
• Use regular power supply network dense power
  grid
• Avoid gaps in grid cause current to flow around
  gap, increases loop area and L
• On-chip L important in wires where speed-of-light
  flight time gt rise times or wire RC delay

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Wire Lengths with Important L

• Inductance important
• Delay of low-resistance signals wide clock
  lines power supply
• With faster edge rates, important for more
  signals
• Inductive crosstalk important for wide busses far
  from current return paths

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Example

• Find skin depth for signals with 100 ps edge
  rates on Cu wires (r 1.7X10-8 Wm)
• 100 ps edge rates mean 1.67 GHz

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Example

• Compute velocity of signals on a metal2 signal
  line and plot lengths where L matters as f (rise
  time)

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Power Distribution Network

• If part of chip requires rapidly increasing
  current
• Charge must come from nearby coupling Cs or
• Supply pins
• Parts of chip further away cannot see increased
  current needs until speed-of-light flight time
  has elapsed
• Cannot supply current immediately
• Inductance in clock lines increases propagation
  delay and sharpens edge rate

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Example

• 5 mm metal6 clock line above metal5 ground plane
• Drives 2pF clock load
• Width4.8 mm, so
• r 4 W/mm
• c 0.4 pF/mm
• L 0.12 nH/mm
• Model with inductance
• Greater delay until clock rises because of
  speed-of-light flight time
• Overshoots
• Sharper rising edge
• Shorter rise time

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Example
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Design to Reduce L and Skin Effect

• Split wide wires into thinner sections
  interdigitated with VDD and Ground to serve as
  return paths

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DFT to Reduce L

• Closely spaced bus of wires high above Ground
• Very susceptible to inductive crosstalk
• Example If all but 1 bus wire rises, each loop
  induces a magnetic field
• Fields pass through loop formed by non-switching
  wire
• Not practical to solve for large chip
  interconnect
• Follow design rules, instead
• Insert 1 VDD or Ground wire for every N signal
  wires
• N is signalreturn ratio
• N 4 is sufficient for 180 nm processes
• N 2 means each signal is shielded on 1 side
• Eliminates ½ of capacitive crosstalk expensive
• Regular VDD and Ground plane with no gaps
  essential
• Interdigitate VDD and Ground in wide signal lines
  (clock)
• Simulate L in power and clock networks

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Temperature Dependence

• C independent of T
• R varies strongly
• For Cu or Al wire, 0.4/ºC temperature
  coefficient
• Example
• 100ºC increase in T increases R by 40

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Effective R and Elmore Delay

• Model Gate with effective R and C has t RC
• Wire with distributed R and C as p-segment has
  t RC/2

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Calculations

• Distributed C circuit
• C charged (on average) through R/2, so half the
  delay
• Actual tpd 0.38 RC
• Elmore model describes distributed delay well if
  using Reff 0.69 R?
• Delay depends on input rise time
• Approaches RC in lumped case, RC/2 in distributed
  case

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Simulations
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RC Tree

• Use for wire branching to many places, instead of
  RC ladder
• Elmore delay to node i

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Example

• Find Elmore delay from input x to each receiver

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Summary

• Fringing Field Capacitance
• Crosstalk
• Crosstalk Delay
• Crosstalk Noise
• Inductance Important for bond wires to package
  and signal integrity
• Now important for internal chip interconnect