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Inspektor Test Jagt Defekte

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1984-95 IBM, Poughkeepsie/East Fishkill NY. 1995-99 ... Scribe-line (KERF) monitors. Dedicated monitor structures. On-chip monitors (e.g., PSRO, etc. ... – PowerPoint PPT presentation

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Title: Inspektor Test Jagt Defekte


1
Inspektor Test Jagt Defekte
  • Dr. Bernd Koenemann

Testviewz.com 2007
2
About Me
  • 1974 Diplom-Physiker, TU Braunschweig
  • 1977 Dr. rer. nat., TU Braunschweig
  • 1978-80 RWTH Aachen (ITHE, Prof. W. Engl)
  • 1980-84 Honeywell, Minneapolis MN
  • 1984-95 IBM, Poughkeepsie/East Fishkill NY
  • 1995-99 LogicVision, San Jose CA
  • 1999-02 IBM, San Jose CA
  • 2002-04 Cadence Design Systems, San Jose CA
  • 2004-05 Mentor Graphics, San Jose CA
  • 2005- Dolce Far Niente, San Jose CA/Cartagena
    de Indias

3
Web-Presence
  • Professional
  • http//www.testviewz.com
  • Presentations, papers
  • Personal
  • http//www.koenemann.org
  • Photos, videos, music

4
Overall Context
5
Why Do We Need Manufacturing Test?
Perfectby design
Defects !!!
6
Defect Types and Potential Sources
Static
Environmental (Vdd, T, PLL, SEU)Coupling Noise,
Signal IntegrityHotE, Electromigration, Negative
Bias Threshold Instability (NBTI)
? Particle and otherSingle Event Upsets (SEU)
Dynamic
From R.Puri, IBM
7
Static Variability
  • Overall static variability is on the rise

From S. Nassif, ISPD 2004
8
Dynamic Variability
  • Voltage
  • Activity change
  • Power deliveryRLC
  • Dynamicns to 10-100 uSec
  • Within die
  • Temperature
  • Change in activity and ambient
  • Dynamic 100s of uSec to mSec
  • Within die

9
Design Changes Due to Variability
System
Logic
Circuit
Deterministic
Layout
Models
Manu-facturing
Characterization
From R.Puri, IBM
10
What Does That Mean?
  • Yield limiters may buried inside the product
    design
  • Very context-sensitive and design specific
  • Non-visual and not represented in test vehicles

WorstCaseSpec
StatisticalSpec
EDAModel
Probability
Parameter
11
Design versus Reality
Manufacturing
Design
Reality Check?
Reality Check?
12
Defect Learning
  • Background
  • Inspection/metrology
  • Test/characterization Vehicles
  • Yield management systems
  • Enhanced learning with test
  • Debug/diagnostics/failure-analysis
  • Statistical processing

13
Inspection/Metrology
  • Scanning for visible defects (mask/wafer)
  • Special equipment
  • Creates defect maps
  • Measurement/tracking of process parameters
  • Metrology equipment for specific process issues
    (e.g., surface planarity, oxide thickness, etc.)
  • Equipment logs
  • Measurement of circuit parameters
  • Scribe-line (KERF) monitors
  • Dedicated monitor structures
  • On-chip monitors (e.g., PSRO, etc.)

14
In-Line Inspection (Surface Scan)
Equipment
Results File
e.g., Defect x-y-coordinates Defect size Defect
classification Etc.
Detailed Image
Wafer Map Image
From Multiple Sources
15
Test Vehicles
  • Simple monitor structures for specific defect
    types
  • E.g., metallization, vias, contacts, etc.
  • Sophisticated design/process characterization
    monitors
  • E.g., multiple defect types, representative of
    design/library elements, etc.

16
Simple Serpentine Test Structure
  • Suitable for measuring metallization defect
    densities

From Hess, et al., 2001
17
Yield Management Systems
  • Infrastructure for monitoring and analyzing yield
    issues
  • Data collection
  • Data warehousing
  • Data mining/analysis
  • Increasingly comprehensive
  • Many data types (e.g., logistics, equipment,
    metrology, binning, etc.)
  • Many analysis routines (e.g., queries, report
    generation, visualization, alert automation,
    etc.)
  • Customizable (e.g., database extensions,
    scripting/APIs, etc.)

18
Example Data Visualization (from Test)
Source, R. Madge, ITC 2004
19
The New Role of Test
  • Classical Yield Management Systems provide lots
    of wafer-level information, but lack intra-chip
    resolution
  • Test observes chip-internal fail behavior that
    could help uncover the statistical impact of new
    catastrophic and parametric defect sources inside
    the chips
  • By adding statistical analysis capabilities, test
    can become a key tool for statistical
    design/yield learning

20
Test and Diagnostics
21
Diagnostics
  • Finding the root-cause of a particular test fail
  • Characterizing the failing behavior
  • Localizing the most likely problem area
  • Integral part of
  • Silicon debug
  • Failure analysis

22
Example
From A. Weber, Semi International, 2004
23
Logic Diagnostics and Failure Analysis
  • Log some number of fail sets from test
  • Run logic fault isolation software
  • Create gate-level callouts (net/pin names, fail
    type) most likely near the problem area
  • Visualize callouts in layout
  • Requires link between gate-level netlist and
    layout (e.g., from running LVS)
  • Overlay callouts with defect maps or other
    information
  • Requires translation to/from wafer-level
    coordinates
  • Initiate Failure Analysis (FA)

24
Fault Isolation Software
Netlist,Fault Models
Fault Simulation
Simulatedfail sets
TestPatterns
Compareandrank
Callouts
ATE/BIST
Fail sets
Note Fault simulation can be run ahead of time
to pre-calculate a fault dictionaryor after the
fact during diagnostics
25
Callout Example
Note from IBM TestBench
26
Logic Bitmapping
Fail Net Visualization
Note from LSI Logic
27
Statistical Diagnostics for Logic
  • Emerging defect/yield learning method for complex
    logic designs
  • Implement comprehensive fail set logging for
    initial ramp and for volume production test
  • Run logic fault isolation on all fail sets (could
    be thousands per day)
  • Write all callout information into database
  • Statistically sort, analyze, and visualize the
    cumulative callout information, e.g.,
  • Query by cell-type, cell-instance/location, etc.
  • Stack results on chip layout, reticle, and/or
    wafer map
  • Compare with yield predictions
  • Etc.

28
Example Stacked Callout Visualization
Note from LSI Logic
29
State of the Art
  • Statistical diagnostics of logic fails are a
    rapidly emerging design/defect learning
    technology
  • Learning design-specific issues from product
    chips
  • Statistical relevance with large number of
    samples
  • Complement/enhance existing fab-oriented yield
    management systems
  • Add intra-chip resolution and visibility
  • Complement/enhance DFM and yield modeling
  • Provide feedback and calibration
  • Most existing solutions are home-grown at IDMs
  • Challenging data security/access issue for
    fabless/foundry
  • No integrated commercial solution yet

30
Vision of an Integrated Solution
Yield Management
Debug/FA Lab
Applications
Applications
APIs/Utilities
APIs/Utilities
Design Database
Data Warehouse
WIP, Metrology, Test,
Design, design analysis,
Inspection, etc.
design intent, etc.
31
The End
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