CPU Organization

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CPU Organization

• AMS-505 Serial 2.4

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Functional Units
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Fundamental Computer Purpose

• To receive and store an ordered list of
  instructions and then to execute these
  instructions when told to do so in a serial (Von
  Neuman) fashion with the end goal of achieving
  something useful to the person(s) who created and
  ordered the list.
• Everything else is icing on the cake.

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CPU

• Function
• To perform the following over and over again
  from the moment power is turned on to the moment
  it is removed
• Fetch an instruction from memory
• Execute that instruction
• Thats it. Period.

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CPU - ALU
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CPU - IR

• The instruction is typically brought in from a
  place in memory (more later) and stored
  temporarily in the CPU in a register called the
  Instruction Register.
• The control block can then read the IR and figure
  out where to get the operands for the ALU, what
  to do with them (the function), and then where to
  put the results.
• How does the CPU know where to get the next
  instruction from?

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CPU - PC

• There is a register in the CPU called the
  Program Counter or PC.
• When your program is first executed, the PC holds
  the address in memory of the first instruction.
• Once the instruction has been fetched from
  memory, the PC is incremented to point to the
  next instruction.

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CPU - Updated
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CPU - GPRs

• Almost all CPUs have internal general purpose
  registers that can be addressed by a programmer
  as a source or destination (or both) in an
  instruction.
• They are very fast compared to external memory.

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CPU - Updated
11
CPU - Memory

• The CPU interacts with the external memory
  through a pair of buffers that are usually hidden
  from the programmer.
• These are the Memory Address Register (MAR) and
  the Memory Data Register (MDR).
• These buffers are connected directly to the pins
  on the chip that carry the address and data
  signals to the external memory.

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CPU - Updated
13
CPU - Address Registers

• CPUs also have address registers.
• Address registers provide flexibility by allowing
  indirect addressing of memory locations.

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CPU - Updated
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Instruction Cycle
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CPU - FPU

• Floating Point Operations.
• Process Information represented in the form of
  scientific notation.
• Allows the CPU to process very large and very
  small numbers.
• Eg)
• n f 10e
• f fraction (mantissa)
• e positive or negative exponent

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FPU - IEEE Standard
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Superscalar Architecture

• Multiple Instruction Pipelines
• General Pipeline
• fetch, decode, execute, store
• Instruction-Level Parallelism
• only if instructions are independent