Sin ttulo de diapositiva

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A BiCMOS pulse discriminator interface for the
LHCb calorimeter
A. Diéguez, D. Gascón, M. Roselló, S. Bota, J.
Samitier
Departament dElectrònica, Sistemes
dInstrumentació i Comunicacions, Universitat de
Barcelona Departament d'Estructura i Constituents
de la Matèria, Universitat de Barcelona Departamen
t d'Electrònica, Universitat Ramon Llull
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MOTIVATION CP VIOLATION
Electromagnetic calorimeter
Muon chamber
Tracking chamber
Hadron calorimeter
photons
e?
muons
??, p
n
Innermost layer ...
...Outermost layer
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SPD SIGNAL
Goal to separate charged particles and photons

• High jiter
• Random signal shape

• Pulse shaping methods discarded
• ?
• Integrate

• Only 83 of signal in 25 ns
• No dead time on integration

• Dual channel

? Full-Custom ASIC ? Minimum area The SPD
front-end manages more than 5000 channels. ?
Signal speed Bunch crossing of 40MHz requires a
fast analogue design (BiCMOS).
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TWO CHANNEL STRUCTURE
Single to differential
Integrator
Track Hold
Pile-up compensation
Comparator
Differential Multiplexer
1 Charged
0 Neutral
Threshold
ck, !ck
Ck generator
Current source
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Signal for 4 charged particles (Threshold is set
to detect the signal of smallest amplitude)
P3
P1
P4
P2
All 4 events are detected without wrong triggers.
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ASIC FRONT-END
SPD PHOTOMULTIPLIER
EXPERIMENT CONTROL SYSTEM
16 CHANNELS. 64 PADS AREA 10 mm2 (aprox.)
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Maximum gain fluctuation of R5900U-M64 ? 5.
Reduction to factor 2 (at least) by channel
calibration and tuning of load resistor of each
PMT channel
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CIRCUIT OVERVIEW INTEGRATOR
Requirements Input signal range
0-250mV Absolute resolution 300?V Linearity
error 5 Dynamic margin 58dB,
10b Bandwidth 200MHz Switch freq 40MHz
Av52.7dB, fc1.38MHz, PM82.57º for fu589MHz
Optical micrograph
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CIRCUIT OVERVIEW T H
Triangular waveform tracking
td1.6ns, Max Op Freq500MHz, DR80?V/ns,
Pedestal3.1mV (for 1V input signal), no hold
mode feedthrough
Optical micrograph
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CIRCUIT OVERVIEW SUBSTRACTOR
Av61.8dB, fc493.9KHz, PM52.14º for fu539MHz
Optical micrograph
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CIRCUIT OVERVIEW COMPARATOR
To ECL

• The parasitic capacitance of pads and measuring
  systems ? testing at a flt 200KHz
• When tested in completed chain it has been
  working successfully at 10 MHz.

Simulated td1.6ns, Max Op Freq500MHz Resolution
lt 1mV
Optical micrograph
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Discriminator channel (I)

• Test with 5 MHz clock due to slow response of
  output multiplexer.
• Input signal is a pulse with exponential decay.
  Its decay constant is 48 ns (4 times the
  scintillator decay time because clock period is
  also 4 times longer than the true clock).
• Final clock should be 20 MHz.

0 Neutral
CH1 channel output CH2 input signal
1 Charged
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TEST BOARDS

• ASIC test board

Output buffers Bandwidth 700 MHz. Input
capacitance 2pF.

• Board for clock and input signal trigger
  generation.

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