CoE EE 00142 Computer Organization Set 2 ALU

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CoE - EE 00142Computer OrganizationSet 2 - ALU

• Ron Hoelzeman

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Arithmetic - Logic Unit ALU

• Does the calculations
• Handles integers
• May handle floating point
• May be separate FPU (math co-processor)

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Arithmetic-Logic Unit ALU

• Performs arithmetic
• add, subtract
• Performs logic
• and, or, invert, complement
• Shifts
• right, left, arithmetic, logical
• Provides result and status

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ALU Inputs and Outputs
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Review Binary Addition
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Review Binary Addition
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ALU - Addition
Could try this as an 8 input, 4 output
combinational logic problem
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Instead - Consider Stages
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Half Adder
Truth Table
Sum - S A0B0 A0b0 Carry out - C A0B0
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Half Adder
Karnaugh Map for S - Sum
Karnaugh Map for C - Carry
Sum - S A0B0 A0b0 A0 ? B0 Carry out - C
A0B0
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Half Adder
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Full Adder
Truth Table
S ABCin ABCin ABCin ABCin C
ABCin ABCin ABCin ABCin
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Full Adder
Karnaugh Map for Sum - S
Karnaugh Map for Carry - C
Sum - S A ? B ? Cin Carry out - C AB ACin
BCin
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Full Adder
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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4 Bit Ripple Carry Adder
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Example Numbers

• 8 bit 2s complement
• 127 01111111 27 -1
• -128 10000000 -27
• 16 bit 2s complement
• 32767 011111111 11111111 215 - 1
• -32768 100000000 00000000 -215

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Conversion Between Lengths

• Positive number pack with leading zeros
• 18 00010010
• 18 00000000 00010010
• Negative number pack with leading ones
• -18 11101110
• -18 11111111 11101110
• i.e. pack with MSB (sign bit)

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Addition and Subtraction

• Normal binary addition circuitry
• Take twos complement of subtrahend and add to
  minuend
• i.e. a - b a (-b)
• Need only addition and complement circuits

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Consider Binary Addition
Assume 5 bits 2s complement arithmetic
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Consider Binary Addition
Assume 5 bits 2s complement arithmetic
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Consider Binary Addition
Assume 5 bits 2s complement arithmetic
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Consider Binary Addition
Assume 5 bits 1s complement arithmetic
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Consider Binary Addition
Assume 5 bits 1s complement arithmetic
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Consider Binary Addition
Assume 5 bits 1s complement arithmetic
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Consider Binary Addition
Assume 5 bits 1s complement arithmetic
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4 Bit 2s Complement Adder
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4 Bit 1s Complement Adder
Note carry ripple doubles
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Constructing anArithmetic Logic Unit
Start with a 1-Bit ALU
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Simple Logical Operations
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If Operation is 0, then Result a AND b If
Operation is 1, then Result a OR b
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Consider a 1 bit Full Adder
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If Op is 0, then Result a AND b If Op is 1,
then Result a OR b If Op is 2, then Result
sum of (a b)
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If we repeat the 1-Bit ALU 32 times
If Op is 0, then Resi ai AND bi If Op is 1,
then Resi ai OR bi If Op is 2, then Resi sum
of (ai bi)
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If Op is 0, then Res a AND b If Op is 1, then
Res a OR b
If Op is 2, and if Binvert is 0, then Res
sum (a b) if Binvert is 1, then Res
sum (a (-b))
Add a 1 into Carryin0 to get 2s comp
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ALU with Zero Detection
Control Lines Function 000 and 001 or 010 ad
d 110 sub
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Example Overflow Logic
Overflow occurs if you add two positive numbers
and get a negative number, etc.
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Common Symbol for ALU
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Addition and Subtraction
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Full Adder - Half Adders
2 delays
3 delays
4 delays
From Z to C is 2 delays for each subsequent stage
or 2N 2
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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4 Bit Ripple Carry Adder
2n2 gate delays (10) for 2s complement (assumes
EOR is 2 delays)
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Ripple Carry Adder
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Carry Lookahead Equations

• C2 G1 P1(G0 P0C0)
• C2 G1 P1G0 P1P0C0
• C3 G2 P2(G1 P1(G0 P0C0)
• C3 G2 P2G1 P2P1G0 P2P1P0C0

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Carry Lookahead Adder
Reduces delay to 6 gate delays
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Carry Lookahead Second Level
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Carry Propagation

• 2s complement best
• 1s complement twice as long
• Significant delay reduction using Carry Look
  Ahead concept
• Example - 64 bit adder - reduced from 130 gate
  delays to 14, or improved by a factor of 8

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Basic MIPS Instructions

• Language of the Machine
• More primitive than higher level languages e.g.,
  no sophisticated control flow
• Very restrictive e.g., MIPS Arithmetic
  InstructionsWe will be working with the MIPS
  instruction set architecture
• similar to other architectures developed since
  the 1980's
• used by NEC, Nintendo, Silicon Graphics, Sony

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MIPS Arithmetic

• All instructions have 3 operands
• Operand order is fixed (destination
  first) Example C code A B C MIPS
  code add s0, s1, s2 (associated with
  variables by compiler)

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MIPS Arithmetic

• C code A B C D E F - A MIPS
  code add t0, s1, s2 add s0, t0,
  s3 sub s4, s5, s0
• Operands must be registers, 32 registers provided

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Registers vs. Memory

• Arithmetic operands must be registers
• Compiler associates variables with registers
• What about programs with lots of variables

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Memory Organization

• Viewed as a large, single-dimension array, with
  an address
• A memory address is an index into the array
• "Byte addressing" means that the index points to
  a byte of memory

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Memory Organization

• Most data items use "words"
• For MIPS, a word is 32 bits or 4 bytes
• 232 bytes with byte addresses from 0 to 232-1
• 230 words with byte addresses 0, 4, 8, ... 232-4
• Words are alignedi.e., what are the least 2
  significant bits of a word address?

Registers hold 32 bits of data
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Instruction Example

• Load and store instruction example
• C code A8 h A8 MIPS code lw t0,
  32(s3) add t0, s2, t0 sw t0,
  32(s3)
• Store word has destination last
• Arithmetic operands are registers, not memory!

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End of Set 2
Set 3