AEPT Cost Modeling with SavanSys

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AEPT Cost Modeling with SavanSys

• Design to Cost and
• Design for Manufacturability Solutions
• for todays complex systems

Chet Palesko January 30, 2003
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Agenda

• SavanSys Overview and Update
• Embedded Passives Enhancements
• SavanSys Demonstration
• AEPT cost modeling

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SavanSys - Answer Systems

• Answer Systems has assumed global sales, support,
  and consulting for SavanSys
• Answer Systems (www.answer-systems.com)
• Previously handled SavanSys for all of Europe
• Key SavanSys personnel moved to Answer Systems
  North America
• European distributor of EDA tools and IP founded
  in 1994

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The Design to Manufacturing Over-the-Wall Problem

• Design and Manufacturing are usually disjoint
• Issues of each often conflict with each other.
• Broken communication leads to excessive
  iterations and sub-optimal designs.
• Problem is getting Worse
• Trend toward increased outsourcing.
• Design complexity growing.
• Technology complexity growing.

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The SavanSys Solution
Manufacturing Model(s)
Design Model(s)
Optimized Product
Analysis with SavanSys includes both design
model(s) and manufacturing model(s) enabling
designers to optimize their products for cost,
yield, and performance across both domains
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SavanSys Inputs Components of the Physical
Virtual Prototype

• Library Data
• Physical component information
• Component cost

• Technology Data
• Placement from layout tools
• Substrate technology info.
• Design rules
• Design constraints (size, shape,)

• Design Data
• Architecture
• Bill of Materials

Physical Virtual Prototype
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SavanSys Product
Cost View
Size Routing View
Yield View
System Virtual Prototype
SavanSys
Thermal View
Electrical View
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SavanSys in the Design Flow
Design Environment

• Product Specification
• Target Costing
• System Partitioning
• Product Design
• Target Cost Tracking Optimization
• PCB Place Route
• CM and Board Fab. Selection and Optimization
• Substrate Cost Optimization (layers, interconnect
  technology, etc.)

Product Specification
u
SavanSys Virtual Prototyping Environment
Component Libraries
v
Product Design
SavanSys Assembly fab. Models
PCB Place Route
w
Board Assembly Substrate Fabrication Models
PCB Fab. Assembly
Manufacturing
Finished Product
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SavanSys Manufacturing Library

• SavanSys Process flows
• Chip Preparation Flows
• Ceramic Ball Grid Array Metallurgical Flip Chip
  Bumping
• Ceramic Pin Grid Array
• Substrate Fabrication Flows
• Embedded Passives Double Sided Printed Wiring
  Board
• Inner Layer Pair Multilayer Printed Wiring
  Board
• Photovia Printed Wiring Board Laser Drilled Via
  Thin Film Substrate
• Plasma Etched Via Printed Wiring Board
• Assembly Flows
• Mixed (SMT, through-hole, wirebond, TAB, flip
  chip)
• Test and Rework Adhesive Flip Chip
• Solder TAB Metallurgical Flip Chip
• Wirebond Through-hole
• Single-sided Surface Mount Double-sided Surface
  Mount

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AEPT Consortium Activities

• Embedded passives enhancements to SavanSys
• Support of two new passive types
• Cost modeling support
• Size routing analysis support for devices on
  routing layers
• Development of web-based high level trade-off
  tool
• Process flows for embedded vs. discrete analysis
• Baseline inner layer pair cost model
• Baseline multi-layer board cost model
• Inner layer pair with C-Ply
• Inner layer pair with Dupont ceramic and laser
  trimming
• Inner layer pair with MacDermid resistors
• Economic analysis of emulators
• Nortel (using web based tool)
• Delphi (using SavanSys)
• HP (using SavanSys)

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SavanSys Embedded Passives Support
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Embedded Passives Economic Drivers

• Higher Substrate Costs
• Higher material costs per layer pair (sort of)
• Additional processing steps per layer pair
• Laser trimming per resistor
• More inner layer pairs
• Lower Component and Assembly Costs
• Cost and yield of replaced discrete passives (per
  device)
• Assembly cost and yield of replaced discrete
  passives (per device)
• Increased board area for more functionality or
  smaller form factor
• Unaffected Costs
• Multi-layer board fab. process
• Chip component cost and yield
• Chip assembly cost and yield (unless scrapping is
  done)

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Inner Layer Baseline Model
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HP Emulator with CPLY Embedded Capacitors
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Delphi Emulator with DuPont Ceramic Resistors
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Break Even Cost Analysis

• Assumptions
• Inner layer pair .936 / board to fab and 1.22
  to put into a muli-layer board
• One additional inner layer pair added
• Discrete passive component and placement cost of
  .03 per device
• Average laser trim cost
• 10,000 units

Cheaper to Embed
Cheaper to use Discrete passives
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Summary

• It is hard to justify embedding passives based on
  economics alone, but other factors such as board
  area, electrical behavior, and improved assembly
  yield are significant.
• The additional cost is less than most people
  think.
• The economics vary drastically based on your
• Fabrication cost
• Assembly cost
• Component cost
• Design cost
• The cost difference continues to shrink as
• Embedded technology moves out of development and
  into the mainstream
• Discrete component and assembly costs level out