Chapter 3 Machine Language Instructions

1
Chapter 3Machine Language Instructions
2
Generic Examples of Instruction Format Widths

Variable Fixed Hybrid

If code size is most important, use variable
length instructions If performance is most
important, use fixed length instructions
3
General Purpose Registers Dominate
1975-1995 all machines use general purpose
registers Expect new instruction set architecture
to use general purpose register
Advantages of registers

registers are faster than memory

registers are easier for a compiler to use
-
e.g., (AB) (CD) (EF) can do multiplies in
any order
vs. stack

registers can hold variables
-
memory traffic is reduced, so program is sped up
(since registers are faster than memory)
-
code density improves (since register named with
fewer bits
than memory location)
4
Addressing Objects Endianess and Alignment

• Big Endian address of most significant IBM
  360/370, Motorola 68k, MIPS, Sparc, HP PA
• Little Endian address of least significant
  Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

little endian byte 0
3 2 1 0
msb
lsb
0 1 2 3
0 1 2 3
big endian byte 0
Aligned
Alignment require that objects fall on address
that is multiple of their size.
Not Aligned
5
Top 10 80x86 Instructions
Rank
Instruction
Integer Average Percent total executed
1
load
22
2
conditional branch
20
3
compare
16
4
store
12
5
add
8
6
and
6
7
sub
5
8
move register-register
4
9
call
1
10
return
1
Total
96
Simple instructions dominate instruction frequency
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Machine Language Instructions

• More primitive than higher level languages
• Very restrictive
• Well be working with the MIPS instruction set
  architecture
• similar to other architectures developed since
  the 1980's
• used by NEC, Nintendo, Silicon Graphics, Sony
• Design goals maximize performance and minimize
  cost, reduce design time

7
MIPS ISA

• MIPS assumes 32 CPU registers (0, . , 31)
• All arithmetic instructions have 3 operands
• Operand order is fixed (destination first in
  assembly instruction)
• Operand of arithmetic instructions are in
  registers
• Simple memory addressing mechanism C code A
  B C D E F - A MIPS code add t0,
  s1, s2 add s0, t0, s3 sub s4, s5,
  s0
• t0, s1, s2, are symbolic names for registers
  (translated to the corresponding numbers by the
  assembler).

Compiler
8
Register Usage Conventions
Registers hold 32 bits of data Register zero
always has the value zero (even if you try to
write it)
9
Memory Organization

• Viewed as a large, single-dimension array, with
  an address.
• A memory address is an index into the array
• A word in MIPS is 32 bits long (4 bytes)
• "Byte addressing" means that the index points to
  a byte of memory.
• 232 bytes with byte addresses from 0 to 232-1
• 230 words with byte addresses 0, 4, 8, ... 232-4
• Words are aligned! (the least 2 significant bits
  of a word address?)

...
10
Load and Store Instructions

• A memory address content of a register an
  immediate constant
• C code A8 h A8 MIPS code lw t0,
  32(s3) // Load word add
  t0, s2, t0 sw t0, 32(s3) //
  Store word
• The compiler stores the address of the first
  element of array A in register s3.
• It is assumed that the value of h is stored in
  register s2.
• Store word has destination last
• Remember arithmetic operands are registers, not
  memory!

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Summary so far

• MIPS loading words but addressing bytes
  arithmetic on registers only
• Instruction Meaningadd s1, s2, s3 s1 lt
  s2 s3sub s1, s2, s3 s1 lt s2 s3lw
  s1, 100(s2) s1 lt Memorys2100 sw s1,
  100(s2) Memorys2100 gt s1

12
Example
swap(int v, int k) int temp temp
vk vk vk1 vk1 temp
swap muli 2, 5, 4 add 2, 4, 2 lw 15,
0(2) lw 16, 4(2) sw 16, 0(2) sw 15,
4(2) jr 31
13
Control Instructions

• Decision making instructions
• alter the control flow,
• i.e., change the "next" instruction to be
  executed
• MIPS conditional branch instructions bne
  t0, t1, Label // branch if t0 ! t1
  beq t0, t1, Label // branch if t0 t1
• Example if (ij) h i j bne s0, s1,
  Label add s3, s0, s1 Label ....

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Control Instructions (Continue)

• MIPS unconditional branch instructions j label
• Example if (i!j) beq s4, s5, Lab1
  hij add s3, s4, s5 else j Lab2
  hi-j Lab1 sub s3, s4, s5 Lab2 ...

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Control Instructions (Continue)

• We have beq, bne, what about Branch-if-less-than
  ?
• New instruction if s1 lt s2 then
  t0 1 slt t0, s1, s2 else t0
  0
• Can use this instruction to build "blt s1, s2,
  Label" can now build general control
  structures
• Note that the assembler needs a register to do
  this, there are policy of use conventions for
  registers

16
Machine Language

• Instructions, like registers and words of data,
  are also 32 bits long
• R-type instruction format
• Example add t0, s1, s2
• registers have numbers, t08, s117,
  s218 000000 10001 10010 01000 00000 100000
  op rs rt rd shamt funct
• I-type instruction format
• Example lw t0, 32(s2) 35 18 9
  32 op rs rt 16 bit number

Source register
Destination register
Op-code extension
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Overview of MIPS

• Simple instructions all 32 bits wide
• Very structured, no unnecessary baggage
• Only three instruction formats
• In branch instructions, address is relative to PC
  (next instruction) bne t4,t5,Label gt PC
  (PC4) Label if t4 t5
• In jump instructions, address is relative to the
  4 high order bits of PC
• Address boundaries of 256 MB.
• Pseudo Instructions are assembly instructions
  that are translated by the assembler into one or
  more MIPS instructions
• Example MOV t0, t1 gt add t0, t1, 0

R I J
18
MIPS 5 Addressing Modes
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Constants

• Immediate instructions (2nd operand is a
  constant)
• addi 29, 29, 4 // Add Immediate
  slti 8, 18, 10 // Set Less Than Immediate
  andi 29, 29, 6 // AND Immediate
  ori 29, 29, 4 // OR Immediate
• To load a 32 bit constant into a register, load
  each 16 bit separatel lui t0,
  1010101010101010 //First "load upper
  immediate" Then must get the lower order bits
  right, i.e., ori t0, t0, 1010101010101010 //
  OR immediate

filled with zeros
1010101010101010
0000000000000000
1010101010101010
0000000000000000
0000000000000000
1010101010101010
OR
1010101010101010
1010101010101010
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To summarize
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Alternative Architectures

• We've focused on architectural issues
• basics of MIPS assembly language and machine code
• well build a processor to execute these
  instructions.
• Design alternative
• provide more powerful operations
• goal is to reduce number of instructions executed
• danger is a slower cycle time and/or a higher CPI
• Sometimes referred to as RISC vs. CISC
• virtually all new instruction sets since 1982
  have been RISC
• VAX minimize code size, make assembly language
  easy instructions from 1 to 54 bytes long!
• Well look at PowerPC and 80x86

22
PowerPC

• Indexed addressing
• example lw t1,a0s3 //
  t1Memorya0s3
• What do we have to do in MIPS?
• Update addressing
• update a register as part of load (for marching
  through arrays)
• example lwu t0,4(s3) //
  t0Memorys34s3s34
• What do we have to do in MIPS?
• Others
• load multiple/store multiple
• a special counter register bc Loop
  decrement counter, if not 0 goto loop

23
80x86

• 1978 The Intel 8086 is announced (16 bit
  architecture)
• 1980 The 8087 floating point coprocessor is
  added
• 1982 The 80286 increases address space to 24
  bits, instructions
• 1985 The 80386 extends to 32 bits, new
  addressing modes
• 1989-1995 The 80486, Pentium, Pentium Pro add a
  few instructions (mostly designed for higher
  performance)
• 1997 MMX is addedThis history illustrates
  the impact of the golden handcuffs of
  compatibilityadding new features as someone
  might add clothing to a packed bagan
  architecture that is difficult to explain and
  impossible to love

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A dominant architecture 80x86

• Complexity
• Instructions from 1 to 17 bytes long
• one operand must act as both a source and
  destination
• one operand can come from memory
• complex addressing modes e.g., base or scaled
  index with 8 or 32 bit displacement
• Saving grace
• the most frequently used instructions are not too
  difficult to build
• compilers avoid the portions of the architecture
  that are slow
• what the 80x86 lacks in style is made up in
  quantity, making it beautiful from the right
  perspective

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Summary

• Instruction complexity is only one variable
• lower instruction count vs. higher CPI / lower
  clock rate
• Design Principles
• Simplicity favors regularity
• Smaller is faster
• Good design demands compromise
• Make the common case fast
• Instruction set architecture
• a very important abstraction indeed!
• Fallacy Most powerful instructions mean higher
  performance
• Repeat Prefix (REP) in 80X86
• Fallacy Write in assembly language to obtain the
  highest performance

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MIPS Software conventions for Registers
0 zero constant 0 1 at reserved for
assembler 2 v0 expression evaluation
3 v1 function results 4 a0 arguments 5 a1 6 a2 7
a3 8 t0 temporary caller saves . . . (callee
can clobber) 15 t7
16 s0 callee saves . . . (caller can
clobber) 23 s7 24 t8 temporary
(contd) 25 t9 26 k0 reserved for OS
kernel 27 k1 28 gp Pointer to global
area 29 sp Stack pointer 30 fp frame
pointer 31 ra Return Address (HW)
Plus a 3-deep stack of mode bits.