A Scalable SoftwareBased SelfTest Methodology for Programmable Processors

1
A Scalable Software-Based Self-Test Methodology
for Programmable Processors

• June 4, 2003
• Li Chen, Srivaths Ravi,
• Anand Raghunathan, Sujit Dey
• ESDAT Lab, Dept. ECE, UC San Diego
• NEC Laboratories America, Inc.

2
IC Test Challenges

• Increasing test cost
• Test cost may surpass fabrication cost by 2014
  (ITRS Roadmap)

High clock speed DSM technology ? At-speed testing
IC/tester performance gap ? Self-test
Diverse design styles ? Adaptability
Increasing design complexity ? Scalability
3
Current Test Practices
Pros
Cons
Scan
Systematic High fault coverage
Overhead Speed test
BIST
At-speed test Low-cost ATE
Overhead Power / yield loss
Functional test
Speed test Low overhead no over-testing
High-cost ATE Manual test writing Low fault
coverage

• Combination of these approaches used in practice
• No one-size-fits-all solution

4
New Test Paradigm SBST
Chen Dey, VTS00, DAC00, TCAD01

• Goal Enabling scalable low-cost at-speed
  self-test for
• Processors
• SoCs containing embedded processors
• Processor
• General purpose computing platform for test
• Addressing cost issues
• Test application At-speed test with low-cost
  testers
• Test generation Systematic test program
  synthesis

5
At-Speed Test with Low-Cost Testers
Traditional Functional Test
Test program
Software-Based Self-Test (SBST)
6
Systematic Test Program Generation

• Approach 1 Randomized instructions
• Shen, Abraham (UT Austin)
• Batcher, Papachristou (Case Western)
• Parvathala, Meneparambil, Linsay (Intel)
• Long test programs low fault coverage
• Approach 2 Software-Based Self-Test (SBST)
• Chen, Dey (UCSD)
• Lai, Krstic, Cheng (UCSB)
• Almukhaizim, Petrov, Orailoglu (UCSD)
• Paschalis et al. (Univ. Piraeus, Greece)
• Corno et al., (Poli. Torino, Italy)
• Deterministic tests targeted at structural faults

7
Contributions of this work

• Defines a systematic methodology for SBST
• Automation of key steps
• Scalable to large processors
• First demonstration on commercial processor
• Xtensa from Tensilica

8
SBST Test Generation Basics
1100
On-chip memory
Test Generation Program
010010
Test Application Program
Test program
Response Analysis Program

• Divide and conquer approach
• Module-level test generation
• Instruction-based test delivery

9
SBST Challenges
Must satisfy instruction- imposed constraints
010010

• Constraint extraction
• Constrained test generation
• Test program synthesis

10
Related Work

• Constraint extraction
• Vishkantaiah, Tupuri, Abraham (UT Austin)
• Extracting structural constraints from RTL code
• Lai, Cheng (UCSB)
• Formal verification-based
• Constrained test generation
• Tupuri, Abraham (UT Austin)
• Virtual constraint circuits (VCC)
• Test Program Synthesis
• Lai, Krstic, Cheng (UCSB)
• Backtrack-based search process to find instr.
  sequence

Challenge Complexity
11
SBST Scalable Test Gen. Methodology
Instruction Set Architecture (ISA)
?m ? M
RTL description of processor
12
Generating Test Program Templates
Case (a) MUT affected by single
instruction Enumerate instr. from ISA
Settable Field
1 load altsgt, ltval1gt 2 load alttgt, ltval2gt 3 nop
nop nop nop 4 add altrgt, altsgt, alttgt 5 store
altrgt, ltrespgt
Single-instruction template
13
Simulation-Based Constraint Extraction
Simulateable model of processor
14
Constrained Test Generation
Input constraint
i1 i2 i3 i4 0 ltval1gt?ltval2gt ltsgt
ltsgt
i1
ltval2gt
o1
i2
Module-Under-Test M
ltval1gt
output VCC
input VCC
o1
i3
ltsgt
o2
i4
seen by test generator

• Dual purposes of VCC
• Enforcing constraints on M
• Facilitating test program synthesis

15
Test Program Synthesis
1. Test patterns Pm,t
ltval1gt ltsgt ltval2gt ef12 10 1002 0200
3 029a 1ac0 8 9213 ...
... ...
16
SBST Scalable Test Gen. Methodology
Instruction Set Architecture (ISA)
?m ? M
RTL description of processor
17
SBST Application Tensilica Xtensa?

• Commercial IP core configurable, extensible
• RISC processor with 5 pipeline stages
• Basic configuration
• 81 core instructions
• 412574 stuck-at faults
• 5248 sequential elements
• Experimental methodology
• ModelSim, SPLUS (Constraint extraction)
• Flextest (Constrained module-level ATPG, fault
  simulation)
• Synopsys DC (VCC synthesis)
• Custom tools for several steps

18
Module-Under-Test (MUT) in Xtensa?
ALU
24962 stuck-at-faults
Logic ops
32
control (random logic)
Result of EX stage
Shifter
logic cone
81 input ports (335 bits)
19
Results Constraint Extraction

• 42 templates x 128 training programs
• RTL simulation 37.8 sec per template

1 1 1 1 1 1 1 1 1 1 2 2 2 2
2 2 2 2 2 2 3 3 3 3 3 3 3 3 3
3 4 1 2 3 4 5 6
7 8 9 0 1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6
7 8 9 0 ----------------------------------------
--------------------------------------------------
--------------------------------------------------
------------- add 0 0 0 0 ---as---
???????? -membus- 1 0 0 ---at--- 1 0 0 xxxxxxxx t
--pc3-- 0 0 0 0 0 0 s 00000000 50020 0 0 0 0
0 0 1 0 00 ---as--- 0 8 0

t10r addx2
0 1 0 0 ---as--- ???????? -membus- 1 0 0
---at--- 1 0 0 xxxxxxxx t --pc3-- 0 0 0 0 0 0 s
00000000 50020 0 0 0 0 0 0 1 0 00 ---as--- 0 9
0

t10r slli 0 0 0 0 ---as---
???????? -membus- 1 0 0 00000000 1 0 0 xxxxxxxx
--pc3-- 0 0 0 0 0 0 s 00000000 50020 0 0 0 0
0 0 0 1 ---as--- 0 ? 0

imm30 imm10r
32-imm40 sra 0 0 0 0 40000f60
???????? -membus- 1 0 0 ---at--- 1 0 0 xxxxxxxx t
--pc3-- 0 0 0 0 0 0 0 00000000 50020 0 0 0 0
0 0 0 1 ffffffff 1 b 0

t10r
0sar40 ...
i11 -------- ---at--- ---at--- 00000000 ---at
---
i36 ----------- 00 00 32-imm40 0sar40
i6 -------- ???????? ???????? ???????? ?????
???
i1 i2 i3 i4 ----------------- add 0 0 0
0 addx2 0 1 0 0 slli 0 0 0 0 sra 0 0
0 0
unknown
constant
one-to-one
transformed
20
Results Constrained ATPG

• Func. testable faults ? 20419 (out of 24962)
• 288 module-level test patterns
• CPU time 283.79 sec (Flextest)
• Projected fault coverage ? 18535 / 20419 90.1

21
Results Test Program Synthesis

• Test program synthesis time 1.45 sec
• Actual fault coverage 95.2 (vs. 90.1)

SBST
Rand. Instr.
instr.
7602
9169
Program size
bytes
20373
25066
Prog. execution time cycles
27248
41844
Fault simulation time hrs
27.5
41.3
Fault coverage
95.2
85.3
Excluding reset/termination code Including
reset/termination code
22
Conclusions
Software-Based Self-Test can enable low-cost,
high-quality functional test

• At-speed self-test with low-cost testers
• Scalable, systematic SBST methodology
• First demonstration on commercial processor
• Complement for
• Scan tests
• Detecting speed defects
• Random functional tests
• Top-off mechanism for improving fault coverage