ENGR 212 / CSCI 310 4 March, 2002

1
ENGR 212 / CSCI 3104 March, 2002

• All slides except those with blue backgrounds
• are taken from John Wakerlys
• Stanford EE 121, Digital Design Laboratory

2
2-input XOR gates

• Like an OR gate, but excludes the case where both
  inputs are 1.
• XNOR complement of XOR

X Y X ? Y XOR (X ? Y) XNOR
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
3
XOR and XNOR symbols
4
Gate-level XOR circuits

• No direct realization with just a few transistors.

5
CMOS XOR with transmission gates
IF B1 THEN Z !A ELSE Z A
6
Parity

• A0 ? A1 ? ? An-2 ? An-1
• n-bit odd parity
• (A0 ? A1 ? ? An-2 ? An-1)
• n-bit even parity
• 74x286 parity generator

7
Parity tree

• Faster with balanced tree structure

8
Comparators

• Not Op Amps
• Inputs
• Pairs of n-bit numbers
• Outputs
• Results of comparison
• GT, EQ, LT
• 74x520 8-bit comparator

9
Logic with Multiplexers

• Implementing a 4-bit circuit with
• 16-to-1 multiplexer
• 8-to-1 multiplexer and some invertors
• Example with a spreadsheet