Parameter Variations and Impact on Circuits and Microarchitecture

1
Parameter Variations and Impact on Circuits and
Microarchitecture

• Shekhar Borkar, Tanay Karnik, Siva Narendra,
  James Tschanz, Ali Keshavarzi, Vivek De
• Circuit Research, Intel Labs

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Outline

• Variations
• Process, supply voltage, and temperature
• Impact of variations on circuits and
  microarchitecture
• Variation tolerance and reduction
• Process, circuit, and microarchitecture
  techniques
• Summary

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Variations
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P, V, T Variations
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Frequency SD Leakage
0.18 micron 1000 samples
30
20X
6
Vt Distribution
0.18 micron 1000 samples
30mV
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Frequency Distribution
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Isb Distribution
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Supply Voltage Variation

• Activity changes
• Current delivery RI and L(di/dt) drops
• Dynamic ns to 10-100us
• Within-die variation

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Temperature Variation
Cache
70ºC
Core
120ºC

• Activity ambient change
• Dynamic 100-1000us
• Within-die variation

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Impact on Circuits and Microarchitecure
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Impact on Path Delays
Path Delay
Path delay variability due to variations in Vcc,
Vt, and Temp Impacts individual circuit
performance and power
Objective full chip performance, power, and
yield Multivariable optimization of individual
circuitVcc, Vt, size
Optimize each circuit for full chip objectives
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Circuit Design Tradeoffs

• Higher probability of target frequency with
• Larger transistor sizes
• Higher Low-Vt usage
• But with power penalty

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Impact of Critical Paths

• With increasing of critical paths
• Both s and m become smaller
• Lower mean frequency

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Impact of Logic Depth
Device I
NMOS
40
ON
PMOS
20
Number of samples ()
Delay
40
20
0
-16
-8
0
8
16
Variation ()
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mArchitecture Tradeoffs

• Higher target frequency with
• Shallow logic depth
• Larger number of critical paths
• But with lower probability

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Variation Tolerance and Reduction
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Forward Body Bias
Router chip with body bias
1.5
1.5
1.2V
1.2V
110

C
110

C
1
1
Normalized
Normalized
operating frequency
operating frequency
450mV
450mV
0.5
0.5
0
0
0
200
400
600
0
200
400
600
Forward body bias (mV)
Forward body bias (mV)
FBB increases circuit frequency SD leakage
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Reverse Body Bias
Total Leakage Power Measured on 0.18m Test Chip
RBB reduces SD leakage Less effective with
shorter L, lower VT, scaling
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Adaptive Body Bias--Experiment
Multiple subsites
Resistor Network
5.3 mm
4.5 mm
1.6 X 0.24 mm, 21 sites per die 150nm CMOS
Technology
150nm CMOS
Number of
21
Die frequency Min(F1..F21) Die power
Sum(P1..P21)
subsites per die
0.5V FBB to
Body bias range
0.5V RBB
Bias resolution
32 mV
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Adaptive Body Bias--Results
100
60
Accepted die
20
0
Higher Frequency ?
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Vcc Variation Reduction

• On die decoupling capacitors reduce DVcc
• Cost area, and gate oxide leakage concerns
• On die voltage down converters regulators

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Temperature Control
Tmax frequency power
Tmax frequency power
Temperature
Temperature
Throttle
Throttle
Time (usec)
Time (usec)

• When temperature exceeds the threshold
• Lower freq (activity)
• Lower Vcc

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Tools Design Methodology
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Impact on Design Methodology
Due to variations in Vdd, Vt, and Temp
Probability
Delay
Deterministic
Deterministic
Probabilistic
Probabilistic 10X variation 50 total power
Frequency
of Paths
of Paths
Delay Target
Delay Target
Leakage Power
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Major Paradigm Shift

• From deterministic design to probabilistic and
  statistical design
• A path delay estimate is probabilistic (not
  deterministic)
• Multi-variable design optimization for
• Yield and bin splits
• Parameter variations
• Active and leakage power
• Performance

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Summary

• Parameter variations will become worse with
  technology scaling
• Robust variation tolerant circuits and
  microarchitectures needed
• Multi-variable design optimizations considering
  parameter variations
• Major shift from deterministic to probabilistic
  design