Chandrasekhar Vemulapally

1
Model Generation and Parameter Extraction Tools
for the VTB Environment

• Chandrasekhar Vemulapally
• September 20, 2005
• Department of Electrical Engineering
• University of Arkansas
• Fayetteville, AR 72701
• http//mixedsignal.eleg.uark.edu

2
Outline

• Introduction
• CMRF
• Modelica Importer
• Semiconductor device models
• Certify (Parameter Extraction tool)
• Conclusions and Future work

3
Introduction

• Motivation for Modeling Tools
• HDL modeling is still programming
• Error prone, tedious, time consuming and
  difficult to debug
• Efficient sharing of models among designers in
  their convenient environments is becoming a major
  requirement
• Concentrate more on modeling and design aspects
  rather than on syntax and semantics
• Language-based and Language-independent tools
  like Paragon address all the above issues

4
Paragon Architecture
5
Abstract Model Representation

• Model information saved in XML/MathML as Common
  Modeling Representation Format (CMRF)
• Independent of specific language/simulator
• Able to capture constructs of popular languages
• XML is used because it is
• extensible
• simple, flexible and structured
• open-source and standardized
• enables easy sharing of models

6
CMRF Model Interchange Format

• Language semantics VHDL-AMS vs CMRF
• generic ( Temperature real 300.0
  --Temperature
• Iss real 1.0e-14
  -- bulk junction saturation current
• q real 1.6e-19
  -- Electronic Charge)
• ltinterfacegt
• ltparameter nameTemperature typereal
  default300.0gt
• ltcommentgtTemperaturelt/commentgt
• lt/parametergt
• ltparameter nameIss typereal
  default1.0e-14gt
• ltcommentgtbulk junction saturation
  currentlt/commentgt
• lt/parametergt
• ltparameter nameq typereal
  default1.6e-19gt
• ltcommentgtElectronic Chargelt/commentgt
• lt/parametergt
• lt/interfacegt
• Which is easier to write / modify in terms of
  syntax ? Which is easier to parse ?
• What if I want to add a process / instance flag ?
  

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Why CMRF ?

• Each line leaving a node represents an
  import/export feature to the destination node
• There are n2 lines total, that is a lot of
  coding for import/export features
• Each software product must only know how to
  interface with CMRF (only n lines)

8
Why CMRF ?

• If a new product is created (F), developers of
  that software can create import/export features
  for it, but the other software products would
  require new import/export features for it,
  drawing programming resources away from their
  current tasks (hard/impossible to do in the
  corporate world)
• If a software product changed its format, any
  other products that export to it may no longer
  work. Also, each software product may need to
  rewrite the importer for that product's new format

9
Paragon-MT
10
MultiTranslator Architecture

• MT acts a plug-in tool for importing Modelica
  models into Paragon
• MT utilizes various grammar modules
• grammar rules and actions are defined
• Model Wizard is a part of the tool
• allows the user to interact with the tool
• additional information can be added
• Connection point, parameters and branch
  information can be altered
• Integration is implemented using Component Object
  Model Interface (COM)

11
XML format and Modelica template
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Modelica Model Import Mechanism
Paragon
HDLs
Model Editors
Technology Managers
XML Database
Model Importers
Code Generators
UDD-code Generator
COM-interface
UDD
MultiTranslator
Native VTB model
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Modelica to UDD
model DCMotor "DC Motor" Real Tq10.0 "Torque
applied at the shaft" Real V20.0 "Voltage
across A B" Real i "Current through terminal
A" Real w "Angular rotor speed" Real J0.5
"The rotor moment of inertia" Real R0.4
"Resistance" Real L 0.0025
Self-inductance Real w0125.664 "Rated
angular speed" Real V0115.0 "Rated voltage"
Real b0.196 "Constant of tough friction"
equation VLder(i)Ri V0/w0w Tq-Jder(w)
V0/w0i-bw end DC Motor
lt?xml version"1.0" ?gt ltmodel name"DCMotor"
version"1.1"gt ltcomment value"DC Motor
generated by MultiTranslator" /gt
ltinterfacegt ltparameter default"125.664"
default_enabled"" name"w0" nature"real"
process_parameter"" unit""gt ltcomment
value"Rated angular speed" /gt lt/parametergt . .
. ltport mode"inout" name"node1"
nature"electrical" type"terminal"gt ltcomment
value"" /gt ltterminal number"0" /gt lt/portgt .
. . lt/interfacegt ltbody name"ArchitectureIdeal"gt
  ltinternal_node name"0_mas" type"mechanical"
/gt ltbranch from"node1" name"branch1"
to"node2"gt   ltquantity default"" name"i"
nature"through" type"current" unit"ampere" /gt
  ltquantity default"" name"V" nature"across"
type"voltage" unit"volt" /gt ltequation
string"iinteg(V-Ri-V0/w0w)/L"gt . . .
lt/equationgt   lt/branchgt . . . 
lt/topologygt lt/bodygt lt/modelgt
Modelica model
! UDD input Model file of DCMotor generated by
Paragon ! This is a machine generated code. !
Generated on Wed, 13 Apr 2005 113203 AM Name
DCMotor Nodes 3 Terminals 3 USE Model
DCMotor0 Model DCMotor0 Tq(((-(J(diff(w))))((
V0/w0)i0))-(bw)) pari((INTEG(((v0-v1)-(Ri0))-(
(V0/w0)w)))/L) pari -pari Tq
UDD model file generated by Paragon
XML representation
14
Results (Drive System)
15
Results (Drive System)
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BSIMSOI Model Topology

• Large Signal topology of
• BSIMSOI, v 3.2 MOSFET model
• 5 external connection points
• 1 internal body node

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BSIMSOI Model ( in Paragon )
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BSIMSOI Model ( in Paragon )
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BSIMSOI Model ( in Paragon )
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SPICE and Spectre results (DC)
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SPICE and Spectre results (Transient)
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SiC JFET/SIT Model

• 3 terminal device
• Operation in Unipolar mode Majority carrier
  device - electrons
• Presence of PN junction causes depletion in
  interface that grows or
• shrinks according to the bias applied

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SiC JFET/SIT Model ( Topology )
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SiC JFET/SIT Model
Channel Current
25
SiC JFET/SIT Model (25 oC)
Measured data
Simulation
Vgs 0v
-1v
-2v
-3v
-4v
Measured data and Simulation results for 25 oC
26
Certify

• Model Characterization
• Extraction of optimum parameter values
• Time consuming process
• Is there a need to automate the process?
• YES!!!

27
Parameter Extraction Methodology
Process Libraries (Model Parameters)
Experimental Setup with DUT
No
Netlists
Simulated model characteristics
Match
Physical DUT Characteristics
Simulator Spectre, ADMS, Saber VTB etc.
Yes
Model equations MAST, VHDL-AMS, Verilog-A
Model with New Parameter Values
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Optimization

• Levenberg Marquardt Algorithm
• Straight Line Fit
• Use simulator-in-the-loop technique

29
simulator-in-the-loop
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Example Characterizing a Diode

• Test Bench Editor
• Experiment Editor
• Analysis Information
• Optimizer Information
• Algorithm Selection
• Parameter Information
• XML database

31
Example Characterizing a Diode

• Test Bench Editor
• Experiment Editor
• Analysis Information
• Optimizer Information
• Algorithm Selection
• Parameter Information
• XML Database

32
Example Characterizing a Diode

• Test Bench Editor
• Experiment Editor
• Analysis Information
• Optimizer Information
• Algorithm Selection
• Parameter Information
• XML Database

33
Example Characterizing a Diode

• Test Bench Editor
• Experiment Editor
• Analysis Information
• Optimizer Information
• Algorithm Selection
• Parameter Information
• XML Database

34
Example Characterizing a Diode

• Test Bench Editor
• Experiment Editor
• Analysis Information
• Optimizer Information
• Algorithm Selection
• Parameter Information
• XML database

35
Extracted Parameters
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Conclusions and Future Work

• BSIMSOI 3.2 model was implemented in one month
• Introducing complicated power device models into
  the VTB environment by leveraging new VTB XML -
  Paragon CMRF formats
• Integrate with VTB for the simulator-in-the-loop
  technology
• Integrating with Model Compilers like ADMS to
  generate SPICE code