VHDL%20and%20Sequential%20circuit%20Synthesis

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VHDL and Sequential circuit Synthesis

• VHDL constructs versus automatic synthesis
• What is synthesis?
• Building blocks
• Issues and example
• Tools and targets

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Hardware Description Language (HDL)

• Describe hardware not software
• Description structure
• Language strong syntax and type declarations
• Start with a block diagram

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HDL Constructs Key Ideas

• Entity
• Architecture
• Port
• Process
• Signal types
• Variable
• Conditionals if, case, next, while
• After, wait (until)
• Component port map
• Generate, block

• Concurrency
• Sequential
• Sensitivity List

Principles are the same for most HDL languages
and all practically used languages
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Multiple Architectures for the same entity
There are many ways to describe the same circuit
Entity COMBO is port (A,B,C in bit D out
bit) End COMBO
architecture EG1 of COMBO is Begin D lt (A nand
B) xor C End EG1
Concurrent equations
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Multiple Architectures for the same entity
Xor described behaviorally inside the process
architecture EG2 of COMBO is Begin process (A,
B, C) begin if (C 0) then D lt A nand
B else Dlt A and B end if end
process end EG2
Entity COMBO is port (A,B,C in bit D out
bit) End COMBO
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Multiple Architectures for the same entity
Mix concurrent statements and processes
architecture EG3 of COMBO is signal T
bit begin T lt A nand B p1 process (T,C)
begin D lt T xor C end process
p1 end EG3
Entity COMBO is port (A,B,C in bit D out
bit) End COMBO
As we see, even for a very small circuit there
are several descriptions possible. In case of
large sequential systems, this number is
extremely large, how to select best? How to
program in such a way that the system will
generate the best?
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What is Synthesis?

• Generate hardware from HDL
• Eg. C lt A nand B gives
• Is it that simple?
• No, it is a very complex process in which time
  and space can be rearranged and trade-offs
  investigated, especially for sequential circuits.

A
C
B
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What is Synthesis?
We use Leonardo Spectrum software at PSU
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Watch out for these statements!

• Time expressions after
• Assert, Text I/O
• Configuration declarations
• Dynamic Loops
• Initial values
• Sensitivity lists

Simulation purpose
Simulation purpose
Affect synthesized structures

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Basic Sequential elements

• Latches
• Cheaper than FFs
• Troubles with timing analysis and synchronization
• Possible implication of undesired latches when
  you assign improper modeling type
• Flip-flops
• Edge sensitive
• Asynchronous and synchronous set and reset

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Descriptions 4s5ng 3atches

• You have to distinguish between combinational,
  latches and synchronized Flip-Flops
• Lack of understanding is a common source of
  errors.
• We will first cover latches,
• Next we will cover flip-flops

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Description with Latches

• Data input D enable LE output Q.

signal D, LE, Q bit ... b1 process (D,
LE) begin if (LE 1) then Q lt D end if
end process
b2 block (LE1) begin Q lt GUARDED D end
block
These are two equivalent descriptions of latch
Observe that these two syntax examples involve
storing the signal in a memory
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Description using Latches
These are two equivalent descriptions
library IEEE use IEEE.std_logic_1164.all entity
LATCHES is port (D1, D2, LE in std_logic Q
out std_logic) end LATCHES architecture EG of
LATCHES is begin b1 block (LE '1') begin
Q lt guarded D1 xor D2 end block end EG

• Example

library IEEE use IEEE.std_logic_1164.all entity
LATCHES is port (D1, D2, LE in std_logic Q
out std_logic) end LATCHES architecture EG of
LATCHES is begin process (D1, D2, LE)
begin if (LE '1') then Q lt D1 xor D2
end if end process end EG
This is Logic Enable NOT clock
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Modeling Latches

• when
• Q lt D when En1 else Q
• ...
• Q lt D when En1 else unaffected(VHDL 93)
• if controlled by Enable

• library IEEE
• use IEEE.Std_Logic_1164.all
• entity Latch is
• port (D, En in Std_Logic Q out
  Std_Logic)
• end Latch
• architecture RTL of Latch is
• begin
• L1 process(D, En)
• begin
• if En1 then Q lt D end if
• end process
• end RTL

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Description using Edge Triggered Flip Flops

• Flip Flop is based on a clock signal.
• Rising/Falling edge triggered.

signal D, Q, clk bit .... process
(clk) begin if (clkevent and clk1) then Q
lt D end if end process
Rising edge
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Description using Edge Triggered Flip Flops with
complex excitation function

• Example

library IEEE use IEEE.std_logic_1164.all entity
FLIPFLOP is port (D1, D2, clk in std_logic Q
out std_logic) end FLIPFLOP architecture EG
of FLIPFLOP is begin process (clk) begin
if (clkevent and clk'1') then Q lt D1 xor
D2 end if end process end EG
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Descriptions of Synchronous Set/Reset Flip Flops

• Data and reset is NOT on sensitivity list.

signal D, Q, clk, reset bit ... process
(clk) begin if (clkevent and clk 1) then
if reset 1 then D lt 0 else
Q lt D end if end if end process
D is symbol of next state, not current state
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Synchronous Set/Reset Flip Flops

• No sensitivity list.

signal D, Q, clk, reset bit ... b3 block
(clkevent and clk1) begin Q lt GUARDED 0
when reset 1 else D end block
Role of GUARDED in synchronous FF
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Synchronous Set/Reset Flip Flops

• Example

library IEEE use IEEE.std_logic_1164.all entity
FLIPFLOP is port (D1, D2, reset, clk in
std_logic Q out std_logic) end
FLIPFLOP architecture EG of FLIPFLOP is begin
process (clk) begin if (clk'event and
clk'1') then if reset '1' then Q lt
'0' else Q lt D1 xor D2
end if end if end process end EG
Synchronous reset
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Asynchronous Set/Reset Flip Flops

• Reset is ON sensitivity list.

signal D, Q, clk, reset bit ... process (clk,
reset) begin if (reset 1) then Q lt 0
elsif (clkevent and clk 1) then Q lt
D end if end process
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Asynchronous Set/Reset Flip Flops

• And now full Example of asynchronous ff with
  excitation equation for D

library IEEE use IEEE.std_logic_1164.all entity
FLIPFLOP is port (D1, D2, reset, clk in
std_logic Q out std_logic) end
FLIPFLOP architecture EG of FLIPFLOP is begin
process (clk, reset) begin if reset '1'
then Q lt '0' elsif (clk'event
and clk'1') then Q lt D1 xor D2
end if end process end EG
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Clock Enable Flip Flops
enable
signal D, Q, enable, clk bit ... process
(clk) begin if (clkevent and clk1) then if
(enable1) then Q lt D end if end if
end process
D
Q
D
clk
b4 block (clkevent and clk1) begin Q lt
GUARDED D when enable1 else Q end block
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Flip Flops inferred by Wait Until
signal D, Q, clk bit ... process begin wait
until clkevent and clk1 Q lt D end
process

• No sensitivity lists
• No asynchronous reset

D
D
Q
clk
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Avoid undesired memory elements

• Assign values to variables before using them
• a b and c
• d a or b
• -- combinational network
• Assign value in each branch to signals
• Assign value to signals at the beginning of the
  process

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Flip Flops inferred by Variables
architecture EG of FLIPFLOP is begin process
(clk) variable a,b std_logic begin if
(clk'event and clk'1') then Q lt b
b a a D end if end
process end EG
This assignment of signal needs to have a FF with
output a
Here variable b has no value, it is created only
after a has value and a only after D has value

• We obtain a 3 bits shift register
• Explain why it is so

This is strange
For every variable we have a ff.
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Flip Flops inferred by Variables
architecture EG of FLIPFLOP is begin process
(clk) variable a,b std_logic begin if
(clk'event and clk'1') then a D
b a Q lt b end if end
process end EG
The only difference here is order of assignments
in process, here we have variable assignments
first.
Remember that variables are assigned immediately

• Variable assignment order FF created when
  assigned before use.

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Edge Synchronization using function RISING_EDGE

• Synchronized D Flip-Flop
• Edge Detection
• Clock in sensitivity list...If CLKEVENT and
  CLK1 then ...
• Process with no sensitivity list...wait until
  CLKEVENT and CLK 1

• In simulation X -gt 1 ???
• FUNCTION rising_edge (SIGNAL s std_ulogic)
  RETURN BOOLEAN IS
• BEGIN RETURN (s'EVENT AND
  (To_X01(s) '1') AND (To_X01(s'LAST_VALUE)'0
  ')) END

Here we declare function rising_edge
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Flip-flop with synchronous reset

• architecture dFF_a of dFF is
• begin
• dFF_Lbl process(Clk)
• begin
• if Clk'event and Clk'1' then
• if Reset '1' then
• Q lt '0'
• else
• Q lt D
• end if
• end if
• end process dFF_Lbl
• end dFF_a

• entity dFF is
• port(Reset in Bit
• D in Bit
• Clk in Bit
• Q out Bit)
• end dFF

Earlier we showed another way of using
synchronous reset
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Asynchronous set and reset

• entity dFF is
• port(Reset in Bit
• D in Bit
• Clk in Bit
• Q out Bit)
• end dFF

• architecture dFF_a of dFF is
• begin
• dFF_Lbl process(Clk, Reset)
• begin
• if Reset '1' then
• Q lt '0'
• elsif Clk'event and Clk'1' then
• Q lt D
• end if
• end process dFF_Lbl
• end dFF_a

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Why so many FF syntax?

• Highlight the importance of writing good HDL code
• Coding style affects synthesized structure
  directly
• Internal working of synthesizers

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Descriptions of Tristate Buffers

• 3 output states 0, 1, Z (high impedance)

entity tristate is port ( D, en in std_logic
Q out std_logic) end tristate
architecture EG of tristate is begin Q lt D
when en 1 else Z end EG
p1 process (en, D) begin if (en1) then
Q lt D else Q lt Z end if end
process
Observe that because I used symbol Z the system
inferred tri-state circuit by itslef
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Description of wired circuit using Tristate
Buffers

• Simultaneous assignment to 1 signal
• Does not verify exclusivity

We do not specify if this is wired OR or wired
AND or what
library IEEE use IEEE.std_logic_1164.all entity
tristate is port ( D1, D2 , en1, en2 in
std_logic Q out std_logic) end
tristate architecture EG of tristate is begin
Q lt D1 when en1 '1' else 'Z' Q lt D2 when
en2 '1' else 'Z' end EG
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Flip-flops with Tristate Buffers

• If output of FF or latch is tristated, enable
  line is also tristated.

entity tristate is port ( D, en, clk in
std_logic Q out std_logic) end
tristate architecture EG of tristate is begin
process (en, clk) begin if (en '0')
then Q lt 'Z' elsif (clk'event and clk
'1') then Q lt D end if end
process end EG
This is one more argument for using standard
logic STD_LOGIC
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Tri-State Buffer at the FFs output

• Avoid FF in the path to control the buffer
• architecture DTri_enff of DTri is
• begin
• DTri_Lbl process(Clk)
• begin
• if Clk'event and Clk '1' then
• if TriEnb 0' then
• Dout lt 'Z'
• else
• Dout lt Din
• end if
• end if
• end process DTri_Lbl
• end DTri_enff

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Tri-State Buffer at the FFs output

• library IEEE
• use IEEE.Std_Logic_1164.all
• entity DTri is
• port(TriEnb in Std_Logic
• Din in Std_Logic
• Clk in Std_Logic
• Dout out Std_Logic)
• end DTri
• architecture DTri_encom of DTri is
• begin
• DTri_Lbl process(Clk, TriEnb)
• begin
• if TriEnb 0' then
• Dout lt 'Z'
• elsif Clk'event and Clk '1' then
• Dout lt Din
• end if

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Busses with tri-state buffers

• Use arrays in the declarations

entity tristate is port ( D1, D2 in
std_logic_vector (7 downto 0) en1, en2
in std_logic Q out std_logic_vector (7
downto 0) ) end tristate architecture EG of
tristate is begin Q lt D1 when en1 '1' else
"ZZZZZZZZ" Q lt D2 when en2 '1' else
"ZZZZZZZZ" end EG
This description and circuit describes selector
circuit realized with tri-state buffers on a bus
this is an important circuit
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State Machines

• Finite State Machines (FSM) are a key tool of
  logic design
• A synthesizer can perform state optimization on
  FSMs to minimize the circuit area / delay
• This optimization is only available if the FSM
  model fits templates

State Diagram for Pulse Generator
Timing Diagram for Pulse Generator
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State Machine Example
entity pulseGen is generic ( clkEdge
std_logic '1' edge
std_logic '1') port ( clk, resetn, sig
in std_logic result out std_logic
) end entity pulseGen architecture
state_machine of pulseGen is type states is
(start, waitForSig, found) signal
current_state, next_state states begin
state_logic process(current_state, sig) is
begin case current_state is when
start gt result lt '0'
if sig (not edge) then
next_state lt waitForSig else
next_state lt start end if
when waitForSig gt result lt
'0' if sig (not edge) then
next_state lt waitForSig else
--we have had a transition
next_state lt found end if
when found gt next_state lt start
result lt '0 when others gt
next_state lt start end case
end process state_register process(clk,
resetn) begin if resetn '0' then
current_state lt start elsif clk'event
and clk clkEdge then current_state lt
next_state end if end process end
architecture state_machine
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Implementation of Pulsegen
FPGA Implementation of Pulse Generator
what is state encoding?
State Diagram for Pulse Generator
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Modeling FSM (automata)

• Type of automaton (Moore or Mealy)
• Mix output types of Moore and Mealy
• Synchronisation of outputs in Mealy machines
  (spike elimination)
• Style of modeling the machine
• How many processes (one, two, three)
• State register local variable or signal?
• Clearing and self-correction of automata
• State Minimization
• Encoding
• Concurrent communicating automata
• Hierarchical Automata

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Automaton of Moorea
signal I1, I2, I3 BIT signal RESET, CLK
BIT signal state_reg, next_state
BIT_VECTOR (0 to 2) begin ... process (Clk,
Reset) begin if RESET then
state_reg lt 000 elsif CLK1 and
CLKEvent then state_reg lt
next_stateend if ...

• process (state_reg)
• begin
• case state_reg (0 to 2) is
• when 000 gt Dout lt .....
• if I1 ... then
• Next_state lt ..... end if
• when 001 gt Dout lt .....
• if (I2 and I3)
  ... then
• Next_state lt ..... end if
• end case
• end process

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Automaton of Mealy

• signal RESET, CLK BIT
• signal state_reg, next_state
  BIT_VECTOR (0 to 2)
• ...
• process (Clk, Reset)
• begin
• if RESET then
• state_reg lt 000
• elsif CLK1 and CLKEvent then
  state_reg lt next_stateend if
• end process

• process (state_reg, I1, I2 ...)
• begin
• case state_reg (0 to 2) is
• when 000 gt if (I1 and ...) then
  Next_state lt ..... Dout lt ..... end if
• when 001 gt if (I1 and ...) then
  Next_state lt ..... Dout lt ..... end if
• ....
• end case
• end process

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Finite States Machine
transitions process (present_state, input1)
begin case present_state is when
s0 gt output1 lt '1' if
(input1 '1') then next_state lt s0
else next_state lt s1
end if when s1 gt
output1 lt '0' next_state lt s2
when s2 gt output1 lt '0'
if (input1 '1') then next_state
lt s0 else next_state lt
s2 end if end case end
process end EG
entity test is port ( clk, input1, reset in
bit output1 out bit ) end test
architecture EG of test is type state_type
is (s0, s1, s2) signal present_state,
next_state state_type begin registers
process (clk, reset) begin if
(reset'1') then present_state lt s0
elsif clk'event and clk '1' then
present_state lt next_state end if
end process
Circuit generated
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Finite States Machine

• Moore machine (shown) vs Mealy machine
• State encoding control

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Recommended type of FSM modeling

• STATE_TYPE
• Separate combinational and sequential to two
  processes
• Separate transition function from output function
  (three processes)
• signal state_reg, next_state STATE_TYPE
• signal RESET, CLK BIT
• ....

• - Synchronous state change
• process (Clk, Reset)
• begin
• if RESET then
• state_reg lt S0
• elsif CLK1 and CLKEvent then state_reg
  lt next_stateend if
• end process
• - Excitation and output functions
• process (State_reg, I1, I2, .....)
• begin
• case state_reg is
• when S1 gt Next_state lt .....
• Dout lt .....
• when S2 gt Next_state lt .....
• Dout lt .....
• .....
• end case
• end process

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Finite States Machine

• Case is better than if-then-else
• Others will cause extra logic
• Assign next_state and output in every state under
  every conditions, otherwise latches result.
• Reset is very important. Asynchronous vs
  synchronous

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Output Synchronisation f6r state 0ach5nes

• Outputs in Mealy machine change their states by
  each change of inputs, independently of the clock
• Spikes can be removed synchronizing changes of
  outputs using an additional latch

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Counter with asynchronous read, synchronous reset
and count and no variables in sensitivity list
Counters

• library IEEE
• use IEEE.Std_Logic_1164.all
• use IEEE.std_logic_arith.all
• entity Count is
• port
• (ResetF in Std_Logic
• Clock in Std_Logic
• Count out Unsigned (3
  downto 0))
• end Count

• architecture Count_a of Count is
• signal Count1_s Unsigned(3 downto 0)
• begin
• Count1_Lbl process
• begin
• wait until Clock'event and Clock '1'
• if ResetF '1' then
• Count1_s lt (Count1_s1)
• else
• Count1_s lt "0000"
• end if
• end process Count1_Lbl
• count lt Count1_s
• end Count_a

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Synthesizable model of counter with reading
initial state
Declaration of variable

• library IEEE, COMPASS_LIB
• use IEEE.STD_LOGIC_1164.all
• use COMPASS_LIB.COMPASS.all
• entity OUR_COUNTER is
• port (RESET, CLOCK in STD_LOGIC
• LIMIT in STD_LOGIC_VECTOR (0 to 3)
• COUNT out STD_LOGIC_VECTOR(0to3))
• end entity OUR_COUNTER

• architecture SYNT of OUR_COUNTER is
• begin
• process (CLOCK, RESET) --
• variable cnt STD_LOGIC_VECTOR (0 to 3)
• begin -- specific process construction
• if RESET 0 then asynchronous reset
• cnt 0000 COUNT lt cnt
• elsif CLOCKEVENT and CLOCK 1 then
• -- leading slope of CLOCK used,
• if cnt LIMIT then
• cnt 0000
• elsif cnt cnt 1 -- overloading operator
  
• end if -- for type STD_LOGIC
• COUNT lt cnt
• end if
• end process

Use variable
Change variable to signal
This is behavioral specification which is
synthesizable to FPGAs and perhaps many PLDs
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A word of caution.Hardware realization of VHDL
objects
Implementation of TMP wire
Implementation of TMP latch. Do you real want
it?
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Types / Operators 4 Rules

• Unsigned, signed are arrays of std_logic (just
  like Std_Logic_Vector)
• use closely related type conversion functions to
  convert between above
• My_slv lt std_logic_vector(my_unsigned)
• My_unsigned lt unsigned(my_slv)
• Assignments are still strongly typed, so lhs, rhs
  need to be same length, and this conversion must
  be done
• numeric_std overloads operators for use on types
  signed, unsigned, and their combinations with
  integers. SLV is NOT in the picture.
• Std_logic_vectors have no numeric representation
  at all even when you include the arithmetic
  libraries (numeric_std, or std_logic_arith).
• The only library that lets you treat slvs as
  numbers is std_logic_unsigned (or signed) which
  essentially just does the closely related type
  conversion for you.
• conversion between integer,signed,unsigned is
  done with to_signed, to_unsigned, to_integer

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Lab4 SUPER Simple TB
gen_clk process begin clk lt '1'
wait for 10 ns clk lt '0' wait for 10 ns
end process gen_clk tb PROCESS
variable address unsigned(2 downto 0)
"000" variable opcode unsigned(3 downto 0)
"0000" BEGIN -- wait for
the rising edge of the clock to make it --
easier to interpret on the WAVE window
wait until rising_edge(clk) write_enable lt
'1' adr lt "000" databus lt x"12"
wait until rising_edge(clk) adr lt "001"
databus lt x"01" wait until
rising_edge(clk) adr lt "010" databus lt
x"5a" wait until rising_edge(clk) adr lt
"011" databus lt x"00" -- a x0112,
bx005a wait until rising_edge(clk) adr lt
"100" databus lt x"03" --shift left by 3
wait until rising_edge(clk) adr lt "100"
databus lt x"80" -- add ab wait -- wait
forever END PROCESS -- End Test Bench
- User Defined Section
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Worked Example Statemachines

• Use traffic light example
• Consider two templates

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State Encoding
type traffic_states is (red, yellow, green,
fl_yellow, f_red, turn_arrow ) signal
current_state, next_state traffic_states
Sequential encodes the states as a binary
number (frequently in order of long paths)
000,001,010,011,100,101
Only one flip-flop is active, or hot, at any one
time.
100000, 010000, 001000, 000100, 000010, 000001

• One-Hot - The "One-Hot" encoding option will
  ensure that an individual state register is
  dedicated to one state.
• Only one flip-flop is active, or hot, at any one
  time.
• One-hot encoding is very appropriate with most
  FPGA targets where a large number of flip-flops
  are available.
• It is also a good alternative when trying to
  optimize speed or to reduce power dissipation.

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State Encoding

• Binary code
• Gray code
• Johnson code
• one hot code
• N 0f K code
• Good guess
• Additional software
• Fail safe

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State Encoding

• Compact - The "Compact" encoding option will
  minimizing the number of state variables and
  flip-flops.
• This technique is based on hypercube immersion.
  
• Compact encoding is appropriate when trying to
  optimize area..

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State Encoding

• Gray - The "Gray" encoding option will guarantee
  that only one state variable switches between two
  consecutive states.
• It is appropriate for controllers exhibiting
  long paths without branching.
• In addition, this coding technique minimizes
  hazards and glitches.
• Very good results can be obtained when
  implementing the state register with T or JK
  flip-flops.
• State reg might go 000,001,011,010,110,111

specify encoding style to synthesis tool
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State Encoding
Why might state encoding make a difference? Speed
combinatorial decode of the state variable to
determine outputs and next state can
be made simpler via. one-hot for instance. State
transitions if combinatorial decode of output
is desired to have no glitches, the
encoding makes a difference. Size how many
FFs are required to represent all your states?

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Onehot Encoding
DFFs
High Energy particle may disrupt the state of a
FF leaving us in an illegal state.
readrq
Comb Logic
waiting
readcmd_latch_start
readcmd_latch_wait
readcmd_latch_wehigh

If timing of readrq is such that it is right
before the clock, if delay paths are not matched,
then we could enter illegal state (wait ff could
say Im zero but readcmd.. may not update to
1 Now we are wedged with current state all
zeros.
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Illegal States
given our states (red,yellow,green,fyellow,fred,
turn_arrow)
000
001
010
011
100
101
if they are encoded as above, we have 2 illegal
states. What will logic do when those states
are encountered?
case current_state is when red gt next_State
lt turn_arrow when turn_arrow gt next_state
lt green when green gt next_state lt
yellow. etc.
We dont really know..
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Dealing with State Machine

• Faulty Reset Circuitry (or none) could have you
  power-up in an illegal state
• Single-Event-Upsets in radiation environments can
  cause a flop to toggle, leaving your state
  machine in an illegal state
• Synchronization Errors on inputs
• setup/hold violation
• metastability

Consequences of illegal state entering is
unknown, but frequently result is wedged
machine, which doesnt recover
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Example Machine
SIMPLIFIED Flash Memory reading interface
idea of this is so that external environment can
read flash by simply putting an adr on the line,
and pulling readrq high. The state machine must
go off, and send commands to the flash to get
that piece of data, and the datardy signal will
go high when the data is rdy on the flash pins.
entity flashif is port ( clk in
std_logic -- assume 50 MHz reset
in std_logic -- active low address
in std_logic_vector(22 downto 0) readrq
in std_logic datardy out
std_logic --- signals to flash
iobus out std_logic_vector(7 downto 0)
ale out std_logic cle
out std_logic we out std_logic
re out std_logic ready_busy_b
in std_logic )
79
State Diagram
type state_type is (waiting, -- waits for
readrq readcmd_latch_start, -- steps through
these states once per clock readcmd_latch_wait, re
adcmd_latch_wehigh, -- writes a read
command readcmd_latch_clelow, -- disables the
command latch adr0_latch_start, -- now tells the
flash the address adr0_latch_wait, adr0_latch_wehi
gh, adr9_latch_start, adr9_latch_wait, adr9_latch_
wehigh, adr17_latch_start, adr17_latch_wait, adr17
_latch_wehigh, adr_latch_deassert, waitfor_busy,
-- stays here till flash busy waitfor_notbusy, -
- stays here till flash not busy read_relow, --
tells flash to drive databus read_wait, -- waits
for slow access time read_rehigh -- this
state makes data re go high )
80
Next_State Decoding
statelogic process (current_state,seq_access,rea
drq,sync_busy) begin case current_state is
when waiting gt if readrq '1'
then if seq_access '1' then
next_state lt read_relow
else next_state lt
readcmd_latch_start end if
else next_state lt
waiting end if when
readcmd_latch_start gt next_state lt
readcmd_latch_wait when
readcmd_latch_wait gt next_state lt
readcmd_latch_wehigh when
readcmd_latch_wehigh gt next_state lt
readcmd_latch_clelow when
readcmd_latch_clelow gt etc
Purely combinational process, only 1
output next_state
81
Decoding States for output signals
datardy lt '1' when (current_state read_rehigh)
else '0' -- decode states for re signal
re_reg process(clk,reset) begin if (reset
'0') then re_int lt '1' elsif (clk '1' and
clk'event) then re_int lt next_re end
if end process re_reg re_logic
process(current_state,re_int) begin case
(current_state) is when read_relow gt
next_re lt '0' when read_rehigh
gt next_re lt '1' when others gt next_re
lt re_int end case end process re_logic
Output signals look at current_state to
determine their values. If signal is to be
treated as a clock by outside device, register
it (like re here)
82
Reset Circuitry
statemach process(clk,reset) begin if
(reset '0') then current_state lt
waiting elsif (clk '1' and clk'event)
then current_state lt next_state end
if end process statemach
Without this, state machine may power up in
illegal state (in onehot it almost certainly
will.. since all 0s and and 1s are not valid
states)
83
Dealing with illegal states

• These problems are not specific to Onehot
  encoding.
• They are simply magnified with the scheme, since
  there are far more illegal states!

• Have a reset state obviously
• carefully synchronize all inputs
• If design is in an inaccessible place and can not
  be rebooted..etc.
• Make a safe state machine

use two dff for metastability issues
84
Safe state machines
Others clause is typically not implemented by
the FSM extractor.. (there are no others, since
every one in the ennumerrated type is covered)
The synthesizer may call this the result of
reachability analysis. So it may be up to you
to generate reset logic which will reset the
machine and place it in a known state.
i.e. sync_reset_machine lt 0 when (state a)
or (stateb) else 1 Some synthesis tools
provide attributes for encoding machines that
include safe,onehot safe,grey etc.
This is hit-or-miss though, when REALLY
important. --gt
85
State Machine Example (2)
architecture state_machine of pulseGen is
signal current_state, next_state
std_logic_vector(1 downto 0) constant
start std_logic_vector(current_state'range)
"00" constant waitForSig
std_logic_vector(current_state'range) "01"
constant found std_logic_vector(current_
state'range) "10" constant error
std_logic_vector(current_state'range)
"11" begin state_logic process(current_state,
sig) is begin case current_state is
when start gt result lt '0'
if sig (not edge) then
next_state lt waitForSig else
next_state lt start end if
when waitForSig gt result lt
'0' if sig (not edge) then
next_state lt waitForSig else
--we have had a transition
next_state lt found end if
when found gt result lt '1'
if sig (not edge) then
next_state lt waitForSig else
next_state lt start end if
when error gt result lt '0'
next_state lt start when
others gt next_state lt start
end case end process state_register
process(clk, resetn, next_state) begin
if resetn '0' then current_state lt
start elsif clk'event and clk clkEdge
then current_state lt next_state
end if end process end architecture
state_machine

• Notice the alternative way to define the states,
  as std_logic_vectors.
• There are certain circumstances, such as when a
  circuit will be exposed to a harsh environment,
  when it may not be desirable to allow the
  synthesizer to optimize the state machine
• This optimization may create a state-machine
  where if a single bit of a state register were to
  change, the state machine could enter an invalid
  state and not return.
• By explicitly defining all the states, we remove
  this possibility.
• In general this is NOT need it is recommended
  that enumerated types be used to define states.
• TURN FSM Extraction OFF

86
(No Transcript)
87
Exam Materialall material covered in class,
homeworks, and assigned book chapters is fair ,
however here are some particulars

• you should be able to quickly construct basic
  design elements in synthesizable vhdl.
• e.g. make a d-flipflop w/ enable
• state machines
• simulation vs. synthesis
• mechanics of a process
• given simple design constraints, make
  synthesizable entity/architecture pair

88
Architecture review
architecture behavior of simplecircuit
is component and2 port (a, b in std_logic c
out std_logic) end component signal andout1,
andout2 std_logic begin U6 and2 port map
(a1,b1,andout1) U7 and2 port map
(a2,b2,andout2) sigout lt andout1 or
andout2 end behavior
89
Architecture pieces
begin U6 and2 port map (a1,b1,andout1)
U7 and2 port map (a2,b2,andout2) sigout lt
andout1 or andout2 -- ???? end behavior
component instantiations
CSA conditional signal assigments (though this
one isnt conditional)
process
90
Anatomy of a CSA
sigout lt andout1 or andout2 after 5 ns
From a Modelling Perspective Output events are
created based on input events. Statement is
executed by simulator whenever signals on
right-hand side change This execution may
schedule an event on the left hand side signal
(even at a later time if specified)
91
Anatomy of a CSA
sigout lt andout1 or andout2 after 5 ns
From a Synthesizer Perspective The writer has
written VHDL code that behaves a certain way (in
this case, every time either of the rhs signals
change, sigout will be changed to be equal to the
logical or of the two. Computer As a
synthesizer my goal is to make some hardware that
acts this way also an OR gate will do this but
the synthesizer cant create a precise delay in
any target hardware, thus this is an error.
rewrite as sigout lt andout1 or
andout2 Creating hardware that behaves a
certain way is a difficult job, the writer has to
constrain what he writes so that it is possible
for the synthesis tool.
92
Processes
VHDL domains concurrent domain architecture
describes activities that happen
simultaneously component instances, CSAs,
processes sequential domain -- within a
process describes activities that happen in a
defined order similar to standard programming
languages Definition a process is a series of
sequential statements that must be executed in
order. (talking from simulator perspective)
93
Process anatomy
specifies when to execute the process
process (sensitivity list) declarations begin
statements end process
signals, variables valid inside the process
94
Process Examples
optional label
a
dougs_or process(a,b) begin c lt a or
b end process dougs_or
b
c
weird_or process(b) begin c lt a or b end
process weird_or
a
b
c
What will synthesizer make for case 1? What hw
would you make for case 2? What will synthesizer
make for case 2?
95
Process Examples
examp process(b) begin c lt not b d lt
not c c lt b c lt not b end process
examp
b
c
d
Process Executes in zero time, and signals are
not updated until the process suspends
96
Variables
signals are not useful for storing an
intermediate computation in the middle of a
process, since they are not updated until the
end. For this, we use a variable.
process (x,y,z) variable var_s1, var_s2
std_logic begin var_s1 x and y var_s2
var_s1 xor z sig_out lt var_s1 nand
var_s2 end process
97
Signals
A signal defined at the architecture level is
visible (readable and writeable) in the processes
defined in that architecture.
since variables cant be used outside process,
signals are used to communicate between processes
and CSAs, and components that is, with the rest
of the architecture. In general, use signals for
values that go outside the process, and variables
for things that are just used to compute signal
values. signals represent hardware signals, and
processes are describing a sequence of
computations to determine what values to assign
to those signals.
98
Other process statements
show_if process(a,b) variable a_is_bigger
std_logic begin a_is_bigger 0 if a gt
b then a_is_bigger 1 end if if
ab then dataout lt 11111111 elsif
a_is_bigger 1 then dataout lt a
else dataout lt b end if end process
show_if
show_case process(sel,a,b) begin case sel
is when 00 gt nibble_out lt a(3
downto 0) when 01 gt nibble_out
lt a(7 downto 4) when 10 gt
nibble_out lt b(3 downto 0) when others
gt nibble_out lt b(7 downto 4) end
case end process show_case
99
latching (sometimes accidental)
show_latch process(sel,a,b) begin case sel
is when 00 gt nibble_out lt a(3
downto 0) when 01 gt nibble_out
lt a(7 downto 4) when 10 gt
nibble_out lt b(3 downto 0) end case end
process show_latch
when sel is not one of the three choices
nibble_out stays the same regardless of changing
a,b
could specify default condition nibble_out lt
0000 -- or whatever
100
Latch Inference (Synthesis)

• synthesizer detects signals which are to be
  latched (those that arent assigned under every
  condition
• extract the set of conditions that cause each
  signal to be assigned a value, and use the or of
  those conditions to enable the latch
• done on each signal independently, so each
  process can have a mixture of combinational and
  latched outputs.
• synthesizers typically have a limit of complexity
  for which they can analyze for latching.
• For simplicity and clarity specify latching when
  desired very clearly

if en1 then if sel0 then zlt a else zlt
b end if end if
101
Illustrating Latch Inference
case sel is when 00 gt
nibble_out lt a(3 downto 0) when 01 gt
nibble_out lt a(7 downto 4) when
10 gt nibble_out lt b(3 downto 0)
end case
4
6
7
a(3..0)
1
D0
S1
a(7..4)
S0
2
D1
5
b(3..0)
Y
4
3
D2
4
D3
U11
4
MX4
U10
sel(0)
U9
D
Q
1
nibble_out
A
3
sel(1)
G
Y
2
B
NAND2
DL1
102
Microprocessor I/O port
Registers DDR (Data Direction Register) 1 if
port is an output, 0 if input Output Data
Register if output, value in register is
written to the port
if ddr 1 then outport lt data else
outport lt Z end if
103
Looping to Replicate Hardware
mpu_porta process (ddr,porta_reg) begin for
i in 7 downto 0 loop if ddr(i) 1 then
porta_driver(i) lt porta_reg(i)
else porta_driver(i) lt Z end
if end loop end process mpu_porta
Not necessary to define i, its definition was
implicit (in this case defaulted to integer)
complete form for i in integer range 0 to 7 loop
104
Range Attributes
Specifying loop bounds explicitly is very
inflexible when traversing through an array.
for I in vecrange loop visits elements in the
array from left to right that is, exactly how
you specified the range when defining the
array for I in vecreverse_range loop in reverse
order in which they were specified for I in
veclow to vechigh loop low to high, regardless
of how they were specified
105
For loop (cont)

value must be a constant I.e. no for I in 0 to
current_count loop you may not modify the loop
counter within the loop exit, next solve the
problem of wanting to run through the loop a
variable number of times. I dont recommend
using these much, because as far as I can tell,
the XST synthesizer doesnt handle them well.
Plus, they get confusing as to what hardware you
are making. while loop not synthesizable
106
For loop (example)


begin -- some other stuff here --- carry
'0' BV B for i in 0 to A'left loop
sum(i) A(i) xor BV(i) xor carry carry
(A(i) and BV(i)) or (A(i) and carry) or
(carry and BV(i)) end loop return sum end
107
Exit Statement
entity count_trail is Port (vec in
std_logic_vector(15 downto 0) count out
std_logic_vector(4 downto 0)) end
count_trail architecture Behavioral of
count_trail is begin process(vec)
variable result std_logic_vector(4 downto 0)
begin for i in vec'reverse_range loop
exit when vec(i) '1' result
result "00001" end loop count lt
result end process end Behavioral

16 5-bit full adders 16 5-bit multiplexers (before
any minimization)
next has same syntax and simply skips this
iteration of the loop
108
While Loop Syntax
must have defined range at compile time to be
synthesized
process(vec) variable result
std_logic_Vector(4 downto 0) variable i
integer begin result "00000" i 0
while ilt 16 loop exit when vec(i)
'1' result result 1 i i 1 end
loop count lt result end process
109
Wait Statement

wait reserved word specifies when to suspend
execution of the process and under what
conditions execution is to resume outputs are
recomputed on wait   wait for 20 ns --
suspends the process, and waits for 20 ns.   Wait
on clk,reset -- suspends process until an event
on clk or reset   Wait until enable 1
  You can either use wait statements or a
sensitivity list, NOT BOTH. For the rest of the
class, excluding some special circumstances, I
will use the sensitivity list form.

110
Some Synthesis Limitations

• Process constraints
• no while loops (with variable limits), no simple
  loops (loop forever)
• no incomplete sensitivity lists for comb logic
• no time specs (e.g. wait for 5 ns, altb after 2
  ns)
• see the Menu Edit -gt Language Templates in
  Webpack for examples of how to describe common
  pieces of hardware

111
Registers (FlipFlops)
simple edge-triggered D type Flip-Flop
process(clk) begin if clk1 and clkevent
then Q lt D end if end process
synthesizer also recognizes this template and
will happily build a D-Flop for us.
if rising_edge(clk) then or.. if
falling_edge(clk) then
112
D-Flop variants
process(clk) begin if (clr 0) then
qlt0 elsif rising_edge(clk) then Q lt
D end if end process
?
113
Synchronous Design
In a purely synchronous system, all flipflops in
the design are clocked by the same
clock. Asynchronous Preset / Clear are not used
except for initialization
vs
114
Typical Synchronous System
115
Synchronous System Issues
Why Synchronous Logic? We can reduce the
millions of steps of analysis and timing
verification of our system to a few manageable
ones What is maximum clock frequency that
design can run at? Logic propagation delay
setup time can not exceed time between clock
edges. Clock Skew Identify limited
asynchronous inputs and deal accordingly
luckily this is a pretty easy job for the
synthesizer and pr tools to figure out.
116
Clock Skew
if flops u32 and u33 get clocked significantly
earlier than U34, the value in U33 may be lost,
since by the time U34 is clocked to take U33s
old data, U33s new data has already made it to
its Q output.
117
Global Clock Buffers
Xilinx provides hardware resources to guarantee
negligible clock-skew for limited number of
clocks. Signals for these buffers come in on
special pins or are buffered from the logic via
special cell.
All FPGAs have some sort of solution like this.
Global clocks are obviously limited in number by
the hardware. Making our designs synchronous
also helps us fit into this architecture.
118
Input Synchronization
Synchronize asynchronous inputs to system so that
entire system can be designed in a synchronous
manner.
asynchronous signal
NO
x32
x32
4
U34
1
A
S
3
Y
D
Q
2
B
CLK
U33
MX2
DF1_CC
32 bit wide register
system clk
119
Simple example 2 digit BCD ctr
to get a feel for using processes to make
registers and counters we will design a counter
that will count 2 digits in decimal, for simple
display to a 2-digit LED screen.
library IEEE use IEEE.STD_LOGIC_1164.ALL use
IEEE.STD_LOGIC_ARITH.ALL use IEEE.STD_LOGIC_UNSIG
NED.ALL entity bcdctr is Port ( clk in
std_logic reset in std_logic
en in std_logic bcd out
std_logic_vector(7 downto 0)) end bcdctr
Inputs reset, clock, enable Outputs
LSDigit, MSDigit (4 bits)
120
Simple example 2 digit BCD ctr
this is the hardware that we envision. Knowing
what hardware you want to build is preferable to
cranking VHDL.
architecture behavior of bcdctr is signal mdigit
std_logic_vector(3 downto 0) signal ldigit
std_logic_vector(3 downto 0) begin lcnt
process(clk,reset) begin if reset 0
then ldigit lt 0000 elsif
rising_edge(clk) then if en 1 then
if ldigit 1001 then
ldigit lt 0000 else ldigit lt
ldigit 0001 end if end
if end if end process lcnt
en
ldigit
counter 0-9
clk
en and ldigit 9
mdigit
counter 0-9
clk
121
Simple example 2 digit BCD ctr
en and ldigit 9
mcnt process (clk,reset) begin if
reset'0' then mdigit lt "0000"
elsif clk'1' and clk'event then if
(ldigit"1001") and (en'1') then if
mdigit 1001 then mdigit lt
0000" else mdigit lt mdigit
0001 end if end if
end if end process mcnt bcd(3 downto 0)
lt ldigit bcd(7 downto 4) lt mdigit end
behavior
mdigit
counter 0-9
clk
122
In Webpack (Synthesis Rept)
Synthesizing Unit ltbcdctrgt. Related source
file is C/WINDOWS/Desktop/school/vhdlclass/projec
tsolutions/demo/demo.vhd. Found 4-bit up
counter for signal ltldigitgt. Found 4-bit up
counter for signal ltmdigitgt.
Summary inferred 2 Counter(s). Unit ltbcdctrgt
synthesized.
HDL
Synthesis Report Macro Statistics Counters
2 4-bit up counter
2

123
In Webpack (Rough Timing)
TIMING REPORT NOTE THESE TIMING NUMBERS ARE
ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE
TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT GENERATED AFTER PLACE-and-ROUTE. Clo
ck Information ------------------ ---------------
------------------------------------------------
--- Clock Signal Clock
buffer(FF name) Load -----------------------
------------------------------------------- clk
BUFGP
8 ---------------------------------
--------------------------------- Timing
Summary --------------- Speed Grade -5
Minimum period 6.644ns (Maximum Frequency
150.512MHz) Minimum input arrival time before
clock 6.166ns Maximum output required time
after clock 8.699ns Maximum combinational
path delay No path found Timing
Detail -------------- All values displayed in
nanoseconds (ns)
124
To run functional simulation
125
Enter text commands here
126
In Command Window force signal_name value
(forces an input to be a value) force resetn
0 force databus 11110000 run runtime (advances
simulation time) run 100 ns run 1 sec
127
To force a clock highlight clk signal first,
then Edit-gtClock
128
After forcing clock force reset 0 run 50
Warning There is an 'U''X''W''Z''-' in an
arithmetic operand, the result will be 'X'(es).
Time 0 ps Iteration 0 Instance
/bcdctr force en 0 force reset 1 run 100 force en
1 run 200
129
Sequential VHDLRushton Ch 8

• Processes
• Ref Ashenden Ch5, (for mechanics)
• Edit-gtLanguge Templates (in Webpack)