LECTURE 6: State machines

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LECTURE 6 State machines
EECS 318 CADComputer Aided Design
Instructor Francis G. Wolff wolff_at_eecs.cwru.edu
Case Western Reserve University This
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VHDL Component, Entity, and Architecture
for-generate if generate
Component Instance
Component Declaration
Entity
Architecturei
ConcurrentWith-Select-WhenWhen-Else
OtherConcurrentComponents
ConcurrentBoolean Equations
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VHDL Components
Component Declaration
Optional repeat
COMPONENT component_entity_name GENERIC (
identifier type initial_value )
PORT ( identifier mode type ) END
Component Instance
identifier component_entity_name GENERIC
MAP ( identifier ,identifier ) PORT
MAP ( identifier ,identifier )
mode IN OUT INOUT
type std_logic std_logic_vector(n downto 0)
bit
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VHDL Concurrent Statements
Example y lt NOT ( NOT (a) AND NOT (b) )
Example 2 to 1 multiplexor WITH s SELECT y lt a
WHEN 0, b WHEN OTHERS
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VHDL Concurrent Statements
Conditionial signal assignment
signal lt signal_value1 WHEN condition1
ELSE signal_valuen WHEN
conditionn ELSE signal_valuen1
Example Priority Encoder y lt a WHEN s0 ELSE
b
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SR Flip-Flop (Latch)
Q lt R NOR NQNQ lt S NOR Q
Q lt R NAND NQNQ lt S NAND Q
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SR Flip-Flop (Latch)
Example R lt 1, 0 after 10ns, 1 after
30ns S lt 1
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Gated-Clock SR Flip-Flop (Latch Enable)
Q lt (S NAND LE) NAND NQ
S
NQ lt (R NAND LE) NAND Q
Q
LE
Synchronous Set and Reset
Q
R
Asynchronous Preset and Clear
Latches require that during the gated-clock the
data must also be stable (i.e. S and R) at the
same time
Suppose each gate was 5ns how long does the
clock have to be enabled to latch the data?
Answer 15ns
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Rising-Edge Flip-flop
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Rising-Edge Flip-flop logic diagram
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Synchronous Sequential Circuit
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Abstraction Finite State Machine
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FSM Representations
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Simple Design Example
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State Encoding
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Logic Implementations
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FSM Observations
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Coke Machine Example
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Coke Machine State Diagram
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Coke Machine Diagram II
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Moore Machines
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Mealy Machines