A Robust Celllevel Crosstalk Delay Change analysis

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A Robust Cell-level Crosstalk Delay Change
analysis

• Igor Keller, Ken Tseng, Nishath Verghese
• Cadence Design Systems
• San Jose, CA

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Some Technology Trends

• Interconnect is a key player
• Cc/Ctot, Rline/Rdrv grow
• Timing closure is harder to reach
• Clock cycle smaller
• Tighter margins
• Bigger uncertainty
• Waveform effects important
• Resistive interconnect
• X-Talk
• Skewed gates

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Modern SI-STA problems

• Biggest inaccuracy factors
• Modeling switching aggressors (linear ramp? ?)
• Aggressor selection
• Alignment
• Superposition of noiseless transition and glitch
  ?
• Irregular waveform
• Measurement (slew delay) ? ?
• Downstream effect ?
• Aggressor driver net impedance ? ?
• Linear(ized) driver model
• Ceff Line resistance and x-talk ?
• Non-robustness
• Amplifies small inaccuracy ?
• Discontinuities in results ?

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Today SI-STA must be

• Accurate
• Reference WC realizable setup spice
• Conservative
• Slightly conservative (10)
• Efficient
• Big designs overnight
• Run time linear with number of nets, gates
• Robust with respect to variations of
• Waveforms on aggressors/inputs
• Alignment
• Voltage supply, load on receiver

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Building blocks of new SI-STA
Accurate driver model
Interconnect reduction
Robust delay measurement
PWL wave propagation
Constrained optimization of alignment
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Driver model
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Interconnect
Reduction
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Robust delay measurement
Delay change
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PWL Waveform
10
Alignment optimization
delta
?2
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Delay Change problem formulation

• Stage

• Arrival time

• Delay change

• Receiver Output Probing

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Driver Current Model
accurate
Fast

• Current is a function of voltages
• Like Spice

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ViVo Current Model
Vo
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Standard Cell Library
ViVo models Input and output CCCs Miller and
ground caps

• Propagation of slews

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Interconnect reduction

• RC-network
• Distributed victim aggressors
• Soft-grounded
• Block-Arnoldi
• Proven passivity

Rcv2
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Flow
nets
Fast PWL propagation
nets
arcs
Driver output response
Noise less
Receiver input response
Receiver output response
Aggressor responses
Alignments, receivers
Select alignment
noisy
Driver output response
Receiver input response
Receiver output response
Delay changes
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Fast PWL transition

• BFS traverse of whole design
• One-stage cells
• Driver is modeled using Vivo model
• Multi-stage cells
• Last CCC is modeled using Vivo model
• Slew propagation table till last CCC

VivoSim
Slew prop table from .cdB
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Flow
nets
Fast PWL propagation
nets
arcs
Driver output response
Noise less
Receiver input response
Receiver output response
Aggressor responses
Alignments, receivers
Select alignment
noisy
Driver output response
Receiver input response
Receiver output response
Delay changes
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Driver output noiseless response

• Truncate Z(s) to PI-Load
• 2 ODEs solved efficiently
• 2d order implicit numerical scheme
  (Crank-Nicholson)
• Newton iterations employ predictor-corrector
  idea

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Noiseless response at receiver
j
Voltage Substitution
Y(s) H(s)
j
vj0Hj0.v0
v0
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nets
Fast PWL propagation
nets
arcs
Driver output response
Noise less
Receiver input response
Receiver output response
Aggressor responses
Alignments, receivers
Select alignment
noisy
Driver output response
Receiver input response
Receiver output response
Delay changes
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Voltage and current responses from aggressors
k
S vjk(t-tk)
Si0k(t-tk)
i0
k
k
j
Open circuit voltage
Short circuit current
k
Y (s) H (s)
S vjk(t-tk)
Si0k(t-tk)
i0
k
j
k
Y0k.vk and Hjk.vk are found once for all
alignments!
i0kY0k.vk
vjkHjk.vk
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nets
Fast PWL propagation
nets
arcs
Driver output response
Noise less
Receiver input response
Receiver output response
Aggressor responses
Alignments, receivers
Select alignment
noisy
Driver output response
Receiver input response
Receiver output response
Delay changes
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Driver output response with x-talk
Y (s) H (s)
Iagg
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Noisy response at receiver
j
Voltage Substitution
vj0Hj0.v0
Y(s) H(s)
vj0 Hj0.v0 is found once for each alignment !
j
v0
Linear superposition
S vjk(t-tk)
vj vj0
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ViVoSim accuracy vs. Spice
r200 Ohm xc20 fF
Miller Effect
1.1u/1.5u
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ViVoSim accuracy on path
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Results 40K, 1.3um, 200sec on Linux 2Gh
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Pessimism reduction with ROP
Without Noise
Path delay without noise 4ns Path delay with
noise Rcv Input Probing 8.5ns Rcv Output
Probing 6ns Pessimism reduction 2.5ns!
6ns
RIP
6ns
4ns
3.5ns
ROP
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Path-Based vs Net-Based analysis 0.13um, 500K
instances
Net Based Worst Case Slack -1.56ns
Path Based Worst Case Slack -1.33ns
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Conclusions

• A new delay change analysis is based on
• Current model
• Efficient linear and nonlinear solvers
• PWL waves propagation
• ROP idea
• Nonlinear constrained optimization for alignment
• Accurate
• 2-3 off linear sweep in Spice
• Robust, due to
• Optimization, use of low-pass filter (ROP)
• Reduces pessimism, due to
• ROP, PWL on aggressors
• Fast Less than 1 hour for 1M gates design
• Implemented in CeltIC

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Alignment search

• Nonlinear optimization under constraints
• 2-step process
• Aggressor cluster aligned with victim
• Weighted average of individual alignements
• Refinement per each aggressor
• Rarely needed

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ROP vs RIP slacks
Worst RIP slack -1.56ns
Worst ROP slack -1.33ns
Missing noisy slew annotation?