A Probabilistic Approach to Logic Equivalence Checking

1
A Probabilistic Approach to Logic Equivalence
Checking

• Chun-Yao Wang (???)
• Dept. CS NTHU
• 2006. 01. 06

2
Outline

• Introduction
• Previous Work
• Probabilistic Logic Equivalence Checking
• Exact Approach
• Approximate Approach
• Experimental Results
• Conclusions

3
Motivation

• Logic equivalence checking
• Logic optimization, scan insertion, manual
  modification
• Exhaustively simulation is infeasible for
  practical designs

4
Problem Formulation

• Given two netlists N_ori, N_opt
• N_ori is the original netlist
• N_opt is the netlist after area/timing
  optimization (restructuring)
• The problem is to formally verify the equivalence
  of N_ori and N_opt

5
Outline

• Introduction
• Previous Work
• Probabilistic Logic Equivalence Checking
• Exact Approach
• Approximation Approach
• Experimental Results
• Conclusions

6
Previous Work (1/3)

• Probabilistic based approach
• Assume circuits only consist of AND/OR/NOT gates
• Probability formulae (independent signals)
• Symbol represents the probability of signal one

7
Previous Work (2/3)

• Assign the probability symbol to PIs
• Derive probability expressions
• Perform exponent suppression ( xm? x ) on
  reconvergent gates
• Compare the output probabilities (unique)
• Problem Representation complexity

8
Previous Work (3/3)

• Assign real numbers as input probabilities
  instead of symbols
• Evaluate output probability (number) of circuits
• Arithmetic operations
• Problems
• Aliasing occurrence
• Signal correlation

9
Aliasing Problem

• Two different circuits have the same output
  probability
• Example
• N1N2, but with the same output probability
• Multiple runs increase the confidence level

10
Signal Correlation Problem

• Numbers cannot be assigned immediately
• Numbers should be assigned after exponent
  suppression
• Example
• Two inputs of G2 are correlated with signal B
• Without considering exponent suppression
• Considering exponent suppression

11
Outline

• Introduction
• Previous Work
• Probabilistic Logic Equivalence Checking
• Exact Approach
• Aliasing-Free Probability Assignments
• Encoding Scheme and Alternative Operations
• Dealing with Signal Correlation
• Internal Tree-Structure Replacement
• Approximate Approach
• Experimental Results
• Conclusions

12
Aliasing-Free Probability Assignments

• An aliasing-free assignment
• xi
• ai1(ai-1)21, a1gt3 ? Z, i1n-1
• Problem
• The assignments grow exponentially
• n lt 24 is feasible
• Examples
• x1 , x2 , x3 , , x6
  ,

13
Why Aliasing-Free

• A 3-input function has
  distinct functions
• Assume x1 , x2 , x3
• The probability of each function is distributed
  from

X1 X2
0 0
1 0
0 1
1 1
X3


0
1
14
Encoding Scheme

• Denominators are either ai or the product of ai
• , ,
• Suppose the weight of bit-i is ai
• Multiplication replaces addition
• Reduce memory usage
• Examples
• x1
• x2
• x3
• x1 x2 x3 (
  )

15
Example AND Gate

• Original formulation
• Bitwise-AND (n) operation

16
Shift-Add Operation

• When transforming two input probabilities to
  their equivalent probabilities
• Denominators are either 3, 5, 17, ,
• Shift-add operations are used to obtain the
  numerator instead of multiplication operations
• Example
• Numerator 5 1 5 can be obtained by ( 0001 ltlt
  2 ) 0001 0101 5

( )
( )
17
Example OR Gate

• Original formulation
• Bitwise-OR (?) operation

18
Dealing with Signal Correlation

• When transforming two input probabilities to
  their equivalent probabilities
• The lowest common multiple suppresses the
  correlation of two input probabilities if the
  denominators have the same factor

19
Internal Tree-Structure Replacement

• Example
• Verify if N1 N2
• Only two input assignments and are used

A
A
G1
G1
B
B
G2
G2
C
C
N1
N2
20
Outline

• Introduction
• Previous Work
• Probabilistic Logic Equivalence Checking
• Exact Approach
• Aliasing-Free Probability Assignments
• Encoding Scheme and Alternative Operations
• Dealing with Signal Correlation
• Internal Tree-Structure Replacement
• Approximate Approach
• Experimental Results
• Conclusions

21
Approximation Structure

• Connect Random Probability Generator (RPG) to DUV
• Aliasing-free assignments are assigned to RPGs
  PIs
• RPG produces every possible function
• PO in RPG PI in DUV
• Verify the equivalence of S1 and S2
  Verify the equivalence of L1 and L2

22
Problem Formulation

• Given two large netlists S1, S2 ( of required
  input assignments gt 24)
• The problem is to verify the equivalence of S1
  and S2 with aliasing rate (e)
• e ? pr(S1?S2 n L1?L2)

23
Analysis (1/3)

• Assume r (resource) input assignments are
  available, and S1, S2 (DUVs) have n PIs. What is
  the aliasing rate e in using Approximation
  Structure to verify the equivalence of S1 and S2?
  

24
Analysis (2/3)
L_0 S_0S_15
L_1 S_16S_31
L_2 S_32S_47
L_3 S_48S_63
L_4 S_64S_79
L_5 S_80S_95
L_6 S_96S_111
L_7 S_112S_127
L_8 S_128S_143
L_9 S_144S_159
L_10 S_160S_175
L_11 S_176S_191
L_12 S_192S_207
L_13 S_208S_223
L_14 S_224S_239
L_15 S_240S_255

• r2, n3, connect 2/15, 7/15, 9/15 to the inputs
  of S1
• Uniformly hash 16 S-functions to one L-function
• e ?

25
Analysis (3/3)

• e ? pr(S1 ? S2 n L1 L2)
• pr(L1 L2) - pr(S1 S2) -
• Assume ngt24 ( ), eis simply related to r
• r8, e? 10-77
• r9, e? 10-154
• r10, e? 10-308
• r11, e? 10-616
• r12, e? 10-1233

L1L2
S1S2
26
Outline

• Introduction
• Previous Work
• Probabilistic Logic Equivalence Checking
• Exact Approach
• Approximate Approach
• Experimental Results
• Conclusions

27
Experimental Results exact approach
Circuits PI PO Max ai / Max TFIPI Tree (Y/N) Time (s) Ours / BDD Mem. (MB) Ours / BDD
i9 88 63 13 / 13 N 0.76 / 0.66 6.66 / 6.45
x4 94 71 15 / 15 Y 0.22 / 0.22 5.48 / 5.57
i3 132 6 7 / 32 Y 0.05 / 0.05 3.41 / 4.80
i5 133 66 19 / 19 Y 0.17 / 0.23 5.62 / 5.30
i8 133 81 17 / 17 Y 1.71 / 1.44 11.00 / 10.00
apex6 135 99 22 / 24 Y 0.51 / 0.42 9.50 / 6.23
x3 135 99 23 / 24 Y 1.41 / 0.45 15.00 / 6.52
i6 138 67 5 / 5 N 0.21 / 0.32 5.87 / 5.94
frg2 143 139 23 / 25 Y 2.35 / 0.87 15.00 / 7.63
i7 199 67 6 / 6 N 0.25 / 0.46 6.25 / 6.33
des 256 245 18 / 19 Y 5.23 / 4.42 15.00 / 15.00
28
Experimental Results approximate approach
(r10, e? 10-308)
29
Outline

• Introduction
• Previous Work
• Probabilistic Logic Equivalence Checking
• Exact Approach
• Approximate Approach
• Experimental Results
• Conclusions

30
Conclusions

• An aliasing-free assignment procedure is proposed
  
• More efficient operations, such as bitwise-AND,
  bitwise-OR, and shift-add operations are used
• The aliasing-free assignment and bitwise
  operations deal with the signal correlation
  problem well
• Internal tree-structure replacement is used to
  reduce the number of required input assignments
• An approximate approach with configurable
  aliasing rate is proposed for large circuits

31
Appendix

• P.31P.37

32
Calculate Signal Probability

• Transform two input probabilities to their
  equivalent probability
• The denominator is the lowest common multiple of
  the original denominators
• The two new numerators conduct bitwise-AND/
  bitwise-OR operation to obtain the numerator of
  output probability if it is an AND/OR gates

33
Why Work AND Gate

• The operation 0101n0011 is analogous to perform
  intersection on minterm sets

( )
( )
( )
( )
( )
X2 X1
prob. of minterm
bitwise-AND

• 0 0
• 0 1
• 0
• 1 1

• 0
• 1
• 0
• 1

• 0
• 0
• 1
• 1

• 0
• 0
• 0
• 1

n





34
Why Work OR Gate

• The operation 10001?00101 is analogous to perform
  union on minterm sets

X2 X1
prob. of minterm
bitwise-OR

• 0 0
• 0 1
• 0
• 1 1

• 0
• 1
• 0
• 1

• 0
• 0
• 1
• 1

• 0
• 1
• 1
• 1

?





35
Internal Tree-Structure Replacement (1/2)

• Only consider two Boolean networks for
  verification
• Internal tree-structure replacement can be used
  to reduce the number of required assignments
• The output probability is changed, but it does
  not affect the judgement on the equivalence
  checking

36
Analysis (2/3)

• pr(S1 S2)
• pr(L1 L2)
• If S1S2, then L1L2
• (1) pr(S1 S2 n L1 ? L2) 0
• pr(S1 S2 n L1 L2) pr(S1 S2 n L1 ? L2)
  pr(S1 S2)
• (2) pr(S1 S2 n L1 L2)
• (3) e ? pr(S1 ? S2 n L1 L2) pr(L1 L2) -
  pr(S1 S2) -
• (4) pr(S1 ? S2 n L1 ? L2) 1 pr(L1 L2) 1 -
• (1) (2) (3) (4) 1

L1L2
L1L2
S1S2
S1S2
37
Experimental Setup

• Benchmarks
• nlt24 exact approach MCNC benchmarks in BLIF
  format
• ngt24 approximate approach ISCAS-85 benchmarks in
  BLIF format
• Environment
• SIS environment
• Sun Blade 2500 workstation
• Experimental flow
• Map benchmarks to the SIS library (22-1.genlib),
  decompose the networks to AND/OR/NOT gates
• Verify the equivalence between original Netlist
  and Netlist after area optimization (map m0)
• Separate multiple-output network into many
  single-output subnetworks
• BDD based approach - ntbdd_verify_network( N1,
  N2, DFS_ORDER, ONE_AT_A_TIME )