CS 2200 Lecture 5 Instruction Set Architectures ISAs

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CS 2200 Lecture 5Instruction Set Architectures
(ISAs)

• (Lectures based on the work of Jay Brockman,
  Sharon Hu, Randy Katz, Peter Kogge, Bill Leahy,
  Ken MacKenzie, Richard Murphy, and Michael
  Niemier)

2
Using Stacks

• Basic stack definition
• grows up, grows down
• next empty or last full
• Who saves (caller or callee?)
• Mechanics
• caller at call time
• callee at entry
• callee at exit
• caller after the return

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Stacks

• Stack grows up? down?
• sp points to next empty? or last full?
• Example
• stack grows up (in addresses)
• points to next empty slot
• PUSH(x)
• POP(x)

1006
1005
1004
sp 1003
1003
1002
full items
1001
1000
ADDI sp, sp, 1 SW x, -1(sp)
LW x, -1(sp) ADDI sp, sp, -1
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Stack Conventions
Unix memory layout stack grows down, heap grows
up
4GB-1
stack
unused
heap
data
code
0
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Stack Conventions
4GB-1
stack
unused
64KB-1
unused
LC-2200 layout? no heap. stack grows up. keeps
memory together
heap
data
stack
data
code
code
0
0
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Stack Usage

• RISC machines dont have PUSH/POP instructions,
  you have to do it manually.
• Usually, you dont synthesize PUSH/POP but rather
  do alloc-use-dealloc, e.g

foo addi sp, sp, 2 sw ra, -2(sp)
sw s0, -1(sp) ... lw
s0, -1(sp) lw ra, -2(sp)
addi sp, sp, -2 jalr ra, zero
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Example Leaf Procedure

• int leaf_example(int g, int h, int i, int j)
• int f
• f (g h) - ( i j)
• return f

?
What will be where?
(i.e. how the heck do we do this)
?
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Example Leaf Procedure

• int leaf_example(int g, int h, int i, int j)
• int f
• f (g h) - ( i j)
• return f

For educational purposes, we'll use the s
registers for temporary storage of values. Where
can we put the existing values that are in the s
registers?
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Leaf procedure call revisited
2
foo addi a0, zero, 42 constant
addi at, zero, bar jalr at, ra
jump-and-link ...
halt bar addi sp, sp, 2 alloc
sw ra, -1(sp) save RA sw
s0, -2(sp) save temp addi
s0, zero, 3 temp 3 add v0,
a0, s0 a temp lw s0, -2,(sp)
restore temp lw ra, -1,(sp)
restore RA addi sp, sp, -2
dealloc jalr ra, zero
return!
No need to save ra in leaf procedures
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A-type vs. S-type Temporaries

• s0..s3 temporaries
• s for saved
• callee-saved gotta save em before you can use
  em
• a0..a4 arguments or temporaries
• caller-saved they dont survive a procedure call
  so you save them (as a caller) if you want them
  to survive.
• Why two types? When would you use each type?

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A-type vs. S-type

• Crudely
• S-type for long-lifetime temporaries
• A-type for short-lifetime temporaries
• Ex
• Aside MIPS has T-type as well

void baz() int i, total 0 for (i 0 i
lt 1000 i) total qux(i)
return(total)
int qux(int x) return(2 x 1)
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Leaf procedure call revisited ?
2
foo addi a0, zero, 42 constant
addi at, zero, bar jalr at, ra
jump-and-link ...
halt bar addi sp, sp, 2 alloc
sw ra, -1(sp) save RA sw
s0, -2(sp) save temp addi
s0, zero, 3 temp 3 add v0,
a0, s0 a temp lw s0, -2,(sp)
restore temp lw ra, -1,(sp)
restore RA addi sp, sp, -2
dealloc jalr ra, zero
return!
S-type was a poor choice!
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Leaf procedure call revisited ?
3
foo addi a0, zero, 42 constant
addi at, zero, bar jalr at, ra
jump-and-link ...
halt bar addi sp, sp, 2 alloc
sw ra, -1(sp) save RA sw
s0, -2(sp) save temp addi
a1, zero, 3 temp 3 add v0,
a0, a1 a temp lw s0, -2,(sp)
restore temp lw ra, -1,(sp)
restore RA addi sp, sp, -2
dealloc jalr ra, zero
return!
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Overall Function Call Strategy

• Caller at call time
• put arguments in a0..a4
• save any caller-save temporaries
• jalr ..., ra
• Callee at entry
• allocate all stack space
• save ra s0..s3 if necessary
• Callee at exit
• restore ra s0..s3 if used
• deallocate all stack space
• put return value in v0
• Caller after return
• retrieve return value from v0
• restore any caller-save temporaries

most of the work
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Special Cases

• What to do if there are more parameters than
  registers available for parameters?
• i.e. you have int foo(int a, int b, int c, int d,
  int e, int f, int g, int j, int k)
• but with register conventions, only have a0
  a4 to use to pass in arguments
• Push them onto stack before call

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Arguments and Frame pointer
fp
Addl args Frame Ptr
Addl args Frame Ptr
sp
Arg regs
Ret addr
Other regs
Before function call
Locals
Before Call
After Call
During Call
(Note picture doesnt quite match upcoming
example)
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Example

• Assume we are calling a function with 8
  parameters p, q, r, s, t, u, v, w
• Function will be calling additional functions so
  we need to save all the arguments in a0-a4 on
  the stack

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Example (cont.)

• Caller
• Assume that we have put first five args in
  a0-a4
• add sp, sp, -3 Move stack pointer to
  make
• room for 3 add'l args
• sw s0, 2(sp) Push extra args on stack
• sw s1, 1(sp)
• sw s2, 0(sp)
• jalr s3, ra Assume s3 has address
  of sub
• yada
• yada
• yada

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Example (cont.)

• Callee
• sub
• add sp, sp, -1 Make room on stack for
  old fp
• sw fp, 0(sp) Push old fp onto stack
• add fp, zero, sp Copy current sp into fp
• add sp, sp, -6
• sw ra, 5(sp)
• sw a0, 4(sp) p (also at fp-2)
• sw a1, 3(sp) q (also at fp-3)
• sw a2, 2(sp) r
• sw a3, 1(sp) s
• sw a4, 0(sp) t

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Example

• So
• lw REG, 6(sp) gets old frame pointer
• lw REG, 5(sp) gets return address
• lw REG, 4(sp) gets p etc.
• But what if we move the stack pointer?
• Where is p?
• lw REG, -2(fp)
• (Your complier will be smart and figure this
  out)

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Encoding an instruction set
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Encoding an instruction set

• Must put Add 4, 3, 2 into form the computer
  can understand 1s and 0s
• What this representation ultimately affects
• EVERYTHING! from size of compiled program to
  implementation of the CPU
• Why? CPU must decode the inst. to find out
• What the instruction is and
• what the operands are
• (esp. with regard to addressing modes)

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How is the operation specified?

• Typically in a bit field called the opcode
• Also must encode addressing modes, etc.
• Some options

Variable
.
Operation of operands
Address Specifier 1
Address Field 1
Address Specifier n
Address Field n
Operation
Address Field 1
Address Field 2
Address Field 3
Fixed
Operation
Address Specifier
Address Field
Operation
Address Specifier 1
Address Specifier 2
Address Field
Hybrid
Operation of operands
Address Specifier
Address Field 1
Address Field 2
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Some random comments

• Variable addressing mode allows virtually all
  addressing modes with all operations
• Best when many addressing modes operations
• Fixed addressing mode combines operation
  addressing mode into opcode
• Best when few addressing modes and operations
• Good for RISC
• Hybrid approach is 3rd alternative
• Usually need a separate address specifier per
  operand
• When encoding instructions, of registers and
  addressing modes can affect instruction size

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The gist of instruction encoding

• This is one of those times where you really want
  someone in the class to ask So, what do you
  REALLY need to know about instruction encoding?
• So, Im going to ask myself this question ?
• The answer
• An architect interested in code size rather than
  performance will pick a variable format
• An architect interested in performance will pick
  a fixed format

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Make the frequent cases fast and the rare cases
correct!
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Heres some guidelines

• Make things REGULAR
• The 3 primary components of an instruction set
  are the operations, the data types, and the
  addressing modes
• Keep them orthogonal (or independent) if at all
  possible
• Ex. if you can apply a certain addressing mode
  to 1 operation, you can apply all addressing
  modes to it
• This helps simplify code generation
• Provide primitives, NOT solutions
• In other words, dont target your architecture
  for a specific language. Youre an architect,
  not a compiler writer!

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Guidelines continued

• Simplify trade-offs among alternatives
• Anything designer can do to explain alternative
  code sequences to compiler writer should help to
  improve the code
• Ex. How many times should a value be referenced
  before its cheaper to just put it in a register?
• Provide instructions that bind quantities known
  at compile time as constants
• i.e. if you know the value 3 is going to be
  needed, just include it in some immediate
  instruction

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Example LC 2200
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Instruction Format

• Human Readable
• add s0, s1, a2
• Machine Readable
• 0 9 5 0000 b16
• ADD
• s1 Reg 9
• a2 Reg 5
• unused
• s0 Reg 11 (b16)

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Field NamesR-Type Instruction
unused
rB
rA
op
rD
name
16
4
4
4
4
bits
op opcode rA first register source
operand rB second register source
operand rD register destination operand
How many registers?
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LC-2200 Machine State
(everything is 32 bits wide)
Registers
Memory
0 65535
0 zero 1 v0 2 a0 3 a1 4 a2 5
a3 6 a4 7 a5 8 s0 9 s1 10 s2 11
s3 12 k0 13 fp 14 sp 15 ra
16 x 32-bit words
64K x 32-bit words
PC
32-bit word
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LC-2200 Operations on StateInstructions

• Computation
• Arithmetic ADD, ADDI
• Logical NAND
• Data movement
• load/store LW, SW
• Control Flow
• branch BEQ
• jump-and-link JALR
• Other
• halt HALT

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LC-2200 Instruction Types
all are encoded in single, 32-bit words
R-type Register-Register
31
28
0
19
20
23
24
27
3
4
OP
RA
RB
unused
RD

• How big an immediate?

• How many possible opcodes? How many registers?

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LC-2002 Instruction Set
Arithmetic instructions
R-type Register-Register
31
28
0
19
20
23
24
27
3
4
OP
RA
RB
unused
RD
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LC-2002 Instruction Set
Arithmetic instructions
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LC-2002 Instruction Set
Data movement instructions
A Load from here
A RA Offset
RB ? Mem( )
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LC-2002 Instruction Set
control flow
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Example
Loop until register a0 is zero
loop beq a0, zero, break
addi a0, a0, -1 beq zero, zero,
loop break
0x0030 0x53000002 0x0031 0x233fffff 0x0032
0x500ffffd 0x0033
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LC-2002 Instruction Set
control flow
PC 1
15 1111
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LC-2200 Instructions!

• ADD RD, RA, RB
• NAND RD, RA, RB
• ADDI RB, RA, immed20
• LW RB, immed20(RA)
• SW RB, immed20(RA)
• BEQ RA, RB, immed20
• JALR RA, RB
• HALT

• Whats missing?
• How do you do a NOP?
• How do you subtract?
• How do you branch on an inequality? (e.g. BLT)
• Multiply/divide/shifts
• Data types other than 32-bit words?