Process strainedSi Intels prescot CPU

1
Process strained-Si ( Intels prescot CPU)

• Cap-Layer Ni4Si3 cap
• STI shallow trench insulator
• Source/Drain silicide CoSi2 TiSi2 SiGe
• Process Strained-Si Simulation
• ISE simulation
• Stress ? 0.24 GPa
• ?I ? 10
• First simulation for industry
• process.

Intel 2003 IEDM
2
Mechanically strained-Si

• Low cost
• Package strain

3
Multi-plane Reflector for wafer bonder

Increase the bonder temperature uniformity for 4
in full wafer bonding
 
High reflection on the side of reflector to
compensate the radiation loss at the edge.
4
Wafer Bonding

• To have one initial contact and have only one
  bonding wave
• Bonding on full wafer without defects are
  possible