VEI Meeting Stuttgart

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VEI Meeting - Stuttgart 9/22/99
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Smart Post Bread Board
12v
36v
T1/T2
T3/T4
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Basic construction

• T1/T2 and T3/T4 are packaged together
• Switch consists of 4 pairs of 9 m? 70V FETs
• Vias on FR4 board provide thermal path for FETs
• Copper lugs serve as electrical connection as
  well as heat sink

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Smart Post Inputs

• Alternator status
• Ignition status
• Park status
• Post voltage
• Post current

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Smart Post Outputs

• Direction of current flow through DC/DC converter
• DC/DC converter on/off
• Note These are both open collector outputs.
  Once the form of the control required to direct
  operation of the DC/DC converter is defined,
  these outputs can be modified.

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Additional I/O capability

• 12V and 36V battery temperature
• Power feed for battery temperature sensors
• 12V auxiliary power output
• Ground output
• Status LEDs for current direction and fault
  indication

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Software Development Strategy

• Utilizes rapid control strategy prototyping tools
• State models are graphically input to the PC
• Program generates code, which is downloaded to
  central control module
• Smart post microprocessor acts as drone to
  central control module

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Routinized Control Strategy Development

• Create control strategies with graphical modeling
  tools

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Advantages to Software Strategy

• Allows software and hardware debugging to be
  de-coupled
• Allows real time modifications to code via
  manipulation of state model
• Modules are vehicle worthy, allowing multiple
  iterations of code to be tested

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Central Controller Module
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Smart Post Bread Board Thermal Analysis
Room Temperature Results Rise over ambient
20.0 C P 0.5 watt
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Smart Post Bread Board Thermal Analysis
Elevated Temperature _at_ 105C Rise over
ambient 30 C P 1.0 watt TjC max150 C
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How will production modules differ?

• Optimal thermal performance requires bare die
  construction
• Production FETs will need to be about 1 m?
• Interconnects will need to add about 1 m?
• T3/T4 should be packaged in the DC/DC converter.
• Production location of T1/T2 not defined