PPCH Substrate and PPH Clocks

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PPC/H Substrate and PP/HClocks
John DeHartApplied Research LaboratoryComputer
Science and Engineering Departmenthttp//www.arl.
wustl.edu/arl/projects/techX
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VirtexII Pro Clock Resources

• 16 Clock Pads
• 16 Clock Inputs (IBUFGs)
• represent the clock inputs in VHDL
• 8 Differential Clock Inputs (IBUFGDSs)
• represent the differential clock input pairs in
  VHDL
• Use of any of these replaces/consumes two IBUFGs
  and two clock pads!!
• 16 BUFGMUXs which are either
• BUFG global clock buffer
• BUFGCE global clock buffer with enable
• can turn clocks off when their modules are not in
  use
• 2 versions, one for rising edge clocked circuits
  one for falling edge clocked circuits.
• BUFGMUX global clock multiplexer
• have capability to switch between two clocks
• 2 versions, one for rising edge clocked circuits
  one for falling edge clocked circuits.
• 12 Digital Clock Managers (DCMs)
• deskew and generate clocks as a function of input
  clock
• Backbone
• 24 horizontal and vertical long lines routing
  resources
• Skew minimized by PAR if USELOWSKEWLINES
  constraint is attached to the net.

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VirtexII Pro Clock Resources
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Clock Multiplexer Locations
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Clock Multiplexor Rules

• Rule 1
• BUFGP and BUFGS cannot be used in same quadrant
• They share quadrant routing resources
• So, for example, if BUFG3P is used in Quadrant 1
  , BUFG3S cannot be used in Quadrant 1.
• Hence, if there is a clock that is used in all
  four quadrants its facing clock cannot be used
  at all!
• we need to watch out for this with out 125 MHz
  core clock
• Rule 2
• Adjacent clock multiplexors share two inputs

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DCMs
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DCMs (continued)

• Outputs
• CLK0, CLK90, CLK180, CLK270 phase shifts of
  CLKIN
• CLK2x, CLK2x180 double rate, double rate phase
  shift
• CLKDV CLKIN/CLKDV_DIVIDE
• paramterized clock division
• CLKFX CLKINCLKFX_MULTIPLY/CLKFX_DIVIDE
• parameterized function

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PPC/H Clock Issues

• What clocks do we need and at what frequencies?
• In what quadrants are each of the clocks needed?
• Be aware of LVDS clocks when counting pins/bufs
• they consume 2 pins and/or clock buffers

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PPC/H Substrate Clock Needs Core

• FPGA Core Logic Clock 125 MHz
• 1 IBUFG
• 1 clock pin
• 1 BUFG
• 0 DCMs
• 0 OBUFs

Running Totals IBUFG 1 Clock
pins 1 BUFG 1 DCM
0 OBUF 0
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PPC/H Substrate Clock Needs PP/H

• Interfaces to PP/Hs
• ? IBUFG
• ? clock pin
• ? BUFG
• ? DCMs
• ? OBUFs

Running Totals IBUFG 1 Clock
pins 1 BUFG 1 DCM
0 OBUF 0
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PPC/H Substrate Clock Needs QDR SRAM

• Interface to QDR SRAM
• ? IBUFG
• ? clock pin
• ? BUFG
• ? DCMs
• ? OBUFs

Running Totals IBUFG 1 Clock
pins 1 BUFG 1 DCM
0 OBUF 0
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PPC/H Substrate Clock Needs RocketIO

• RocketIO
• 2 IBUFGDS
• 4 clock pins
• 4 IBUFGs consumed
• 4 BUFGs
• 2 DCMs
• 0 OBUFs

Running Totals IBUFG 5 Clock
pins 5 BUFG 5 DCM
2 OBUF 0
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PPC/H Substrate Clock Needs PPC

• PPC
• Suggested design 0 (PCI Bus design)
• CPU 300 MHz
• PLB 100 MHz
• OPB 100 MHz
• DCR 100 MHz
• DDR 200 MHz
• Ethernet will hang off PCI bus.
• System ACE 33 MHz max
• use same as PCI clock
• PCI 33 MHz max
• use same as for System ACE
• Other Cores (hopefully they all run at least as
  fast as PLB/OPB buses) 100 MHz
• This can be accomplished with
• REFCLK 100 MHz
• 1 DCM
• 3 BUFGs
• CPU Clock (DCM0CLKFX(CLKFX_MULTIPLY3,
  CLKFX_DIVIDE1))
• PLB/OPB/DCR/Cores (DCM0 CLK0)

Running Totals IBUFG 7 Clock
pins 7 BUFG 9 DCM
3 OBUF 2
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PPC/H PP Clock Issues

• Will we support the Power PC on the PP/H?
• If so, how are we going to support SDRAM?

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PPC/H PP Clock Needs Core

• FPGA Core Logic Clock 125 MHz
• 1 IBUFG
• 1 clock pin
• 1 BUFG
• 0 DCMs
• 0 OBUFs

This Page IBUFG 1 Clock pins
1 BUFG 1 DCM
0 OBUF 0 Running Totals
IBUFG 1 Clock pins 1
BUFG 1 DCM 0
OBUF 0
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PPC/H PP Clock Needs Substrate

• Interface to Substrate
• ? IBUFG
• ? clock pin
• ? BUFG
• ? DCMs
• ? OBUFs

This Page IBUFG ? Clock pins
? BUFG ? DCM
? OBUF ? Running Totals
IBUFG 1 Clock pins 1
BUFG 1 DCM 0
OBUF 0
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PPC/H PP Clock Needs QDR SRAM

• Interface to QDR SRAM
• ? IBUFG
• ? clock pin
• ? BUFG
• ? DCMs
• ? OBUFs

This Page IBUFG ? Clock pins
? BUFG ? DCM
? OBUF ? Running Totals
IBUFG 1 Clock pins 1
BUFG 1 DCM 0
OBUF 0
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PPC/H PP Clock Needs RocketIO

• RocketIO
• 2 IBUFGDS
• 4 clock pins
• 4 IBUFGs consumed
• 4 BUFGs
• 2 DCMs
• 0 OBUFs

This Page IBUFG 4 Clock pins
4 BUFG 4 DCM
2 OBUF 0 Running Totals
IBUFG 5 Clock pins 5
BUFG 5 DCM 2
OBUF 0
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PPC/H PP Clock Needs PPC

• PPC
• Whats needed
• CPU 300 MHz
• PLB 100 MHz
• OPB 100 MHz
• DCR 100 MHz
• DDR Shared with Core Logic.
• Ethernet Not used.
• System ACE Not used.
• PCI Not used
• Other Cores
• This can be accomplished with
• REFCLK 100 MHz
• 1 DCM
• 3 BUFGs
• CPU Clock (DCM0CLKFX(CLKFX_MULTIPLY3,
  CLKFX_DIVIDE1))
• PLB/OPB/DCR/Cores (DCM0 CLK0)
• 1 IBUFG
• REFCLK 100MHz

This Page IBUFG 1 Clock pins
1 BUFG 3 DCM
1 OBUF 0 Running Totals
IBUFG 6 Clock pins 6
BUFG 8 DCM 3
OBUF 0
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RocketIO Clock Needs
One of these for Top and one for Bottom. REFCLK
1/20 (Data Rate) for 2.5 Gb/s, REFCLK125 MHz
Xilinx Rocket IO Transceiver User Guide v2.3,
Page 47
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SPI4.2 Sink Clock Needs (Static Alignment)
From Source
To Source
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SPI4.2 Sink Clock Needs (Dynamic Alignment)
From Source
To Source
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SPI4.2 Source Clock Needs
350 MHz for 700 Mb/s
From Sink