TIM: PLD4a

1
TIM PLD4a
(PLD9) l1cnthighstrobe
(PLD9) BCntin
(PLD9) l1cntlowtrobe
(PLD6) EnsaECR2
(PLD6) saECR2
Gate
(PLD6) idECR
12
12
RST
RST
VME data
Counter 0..11
Counter 12..23
VME data
12
(PLD6) idTrig
12
12
12
12
(PLD2) RunMode
12
12
(Reg12) L1IDhi Register
(Reg10) L1IDlo Register
12
VME data
12
VME data
12
12
(FIFO) L1IDL
(FIFO) L1IDH
2
TIM PLD4b
(PLD9) TTypestrobe
(PLD9) TTIDin
(PLD9) BCntin
(PLD9) BCntStrobe
12
10
(PLD6) idBCR
(Reg2A) TTC BCID Register
12
VME data
VME data
10
(PLD2) RunMode
(Reg10) BCID offset Register
Digi Delay
4
4
VME data
10
(PLD6) EnsaBCR2
(Reg16) TTID Register
10
VME data
write
(PLD6) idTrig
RST
(Reg10) BCID Register
Counter
Gate
12
12
VME data
10
(PLD6) saBCR2
12
(FIFO) BCID
(FIFO) TTID
3
TIM PLD7
VME data
Sequencer SRAM circuit shown (Sink version
similar)
8
Switch
Gate
(SRAM) Data
8
8
8
(PLD6) SeqData
4
8
(SRAM) Control
Counter
(Reg1A) Control Register
Control
14
3
2
14
(SRAM) Address
14

Compare
VME data
14
VME address
(PLD2) StartSeq
14
(Reg1C) End Register (Seq Sink)
VME data
(PLD3) SeqBusy
4
TIM PLD9
(From TTCrx)
SubAddr
DQ
DOut
Brcst
BCnt
strobes
SDA
SCL
8
7
12
8
8
4
(Reg2E) TTC Commands Register
8
VME data
4
8
7
Decode ( 0 )
VME data
Brcst2,6
(PLD4b) TType strobe
F/F
2
3
3
BCnt strobes
(Reg28) TTC Select Register
(PLD4a/4b)
VME data
BCntin
12
12
4
clocked thru
4
Compare
8
Latch
82

(PLD4b) TTIDin
En
En
(Reg26) TTC Data Register
VME data
(PLD6) CALin FERin Sparein
8
8
3