A LowEnergy ChipSet for Wireless Intercom

1
A Low-Energy Chip-Setfor Wireless Intercom
DAC 2003 Paper 52.4s

• M. Josie Ammer, Michael Sheets,Tufan Karalar,
  Mika Kuulusa,Jan Rabaey

Berkeley Wireless Research CenterUniversity of
California, Berkeley
2
Overview

• Background
• Application scenario
• System architecture
• BaseBand Processor (BBP)
• Wireless Protocol Processor (WPP)
• Testing
• Results

3
Background

• Scenario
• Ad-hoc voice communication
• Users are physically close, but cannot converse
  normally
• Soldiers in a tank
• Firefighters in a burning building
• Hazardous-material teams in protective suits
• Intercom protocol
• TDMA with up to 20 uplinks
• 64Kbits/s/uplink
• Base station for setup, teardown and framing only
• Any node can be base station
• Remotes communicate peer-to-peer

Intercom Protocol Stack based upon the OSI
Reference Model ISO/IEC 7498-11994
4
System Block Diagram
Clock generation
Wireless Protocol Processor (WPP)
BaseBand Processor (BBP)
Clock generation
SW debug
RS-232
Voltage regulation
2MB flash memory
Voltage regulation
Xilinx FPGA
Dual 8-bit ADC
User interface
RS-232
Off-the-shelf 2.4 GHz RF front-end
Speech codec
Headset
Dual 8-bit DAC

• Intercom protocol stack
• WPP ASIC implementing DLL and higher layers
  control dominated
• BBP ASIC custom digital physical layer data
  path dominated
• RF front-end off-the-shelf analog radio and
  associated circuitry
• Two basic types of computation data path and
  control
• Two design methodologies
• Two custom chips

5
BBP Overview
BBP accommodates relaxed specs for
integrationwith custom low-power analog front-end

• Air interface
• Raw data rate 1.6Mbps
• DSSS length 31 code _at_ 25 Mcps
• QPSK modulation
• Typical indoor frequency-selective wireless
  channel
• Receiver Specs
• /- 100 KHz carrier frequency offset (50ppm from
  2GHz reference)
• 5 dB minimum SNR at ADC
• 50ppm ADC sample clock

6
BBP Design Methodology
Datapath-dominated elements implemented as
heavily-parallelized, direct-mapped ASIC for
energy efficiency

• High-level design exploration in Matlab/Simulink
• Enable early exploration of architectural
  tradeoffs for power, speed, and area
• Parameterized modules in ModuleCompiler
  correspond to fixed-point dataflow blocks in
  Simulink
• In-house design flow, SSHAFT, is direct path from
  Simulink and Module Compiler to ASIC R. Davis
  et al, JSSC March 2002

Module Compiler
VHDL
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BBP Energy Efficient ASIC Flow
Automatic
Control block in Stateflow
VHDL
Enable block in Simulink
Gated clock tree
VHDL
EN
clk2!
EN
clk1!
clk!

• Control used to manage gated clock domains
• Unused blocks are shut off to save energy

8
WPP Overview
WPP implements upper protocol layers using custom
and commercial components in a system-on-chip
architecture

• Architectural components
• Tensilica Xtensa processor
• 64KB program SRAM
• 64KB data SRAM
• 1KB cache
• Custom protocol processing engine
• Flash memory controller
• I/O interfaces
• Sonics SiliconBackplane
• Interfaces
• Two RS-232 serial ports
• Audio port
• External flash memory
• General purpose I/O
• 6-wire interface to BBP

9
WPP HW/SW Co-Design

• Control functionality is mapped onto
  architectural models
• Performance simulations determine requirements
  for the mapping
• Avoid wasted power in over-design
• Find delay requirement gt logic voltage and clock
  frequency

10
WPP Low Power Techniques

• System level
• MAC only listens during TDMA slots of interest
• Physical layer is put in low-power standby mode
  when idle
• Low-power, on-chip SRAM caches entire software
• Clock frequency minimized through performance
  simulation
• Technology level
• Extensive clock gating
• Low core voltage (1.0 V)
• Core and I/O logic have separate supply rails
• Voltage level shifters interface domains allowing
  I/O up to 1.8 V
• Synthesis
• Library characterization incorporated
  low-voltage slow-down factor into synthesis
  constraints
• Preferred gates large gates reduce switching
  capacitance

11
Testing

• Testability features for each chip
• WPP scan chain, BIST, on-chip debug hardware for
  processor
• BBP scan chain, custom test modes
• Testability features on prototype circuit board
• Separation of chips
• Xilinx FPGA used as pattern generator

12
Results
BaseBand Processor (BBP)
Wireless Protocol Processor (WPP)
13
Acknowledgments

• Funding
• DARPA PACC program
• SIA GSRC
• BWRC sponsor companies
• National Technology Agency of Finland
• IP
• Sonics
• Tensilica
• Fabrication
• ST Microelectronics