Continuous Optimization

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Continuous Optimization

• Brian Fahs Todd Rafacz Sanjay J. Patel
  Steven S. Lumetta
• Advanced Computer Systems Group
• Department of Electrical and Computer Engineering
• University of Illinois at Urbana-Champaign

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Continuous Optimization

• Concept
• Optimize instructions in processor pipeline
• Technique
• Streaming table-based optimization hardware
• Motivation
• Reduce dataflow height
• Pre-execute instructions
• Catch branch mispredictions early

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Outline

• Continuous optimizer design
• Performance characterization
• Current work

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Continuous Optimization
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Symbolic Values

• Expression format
• Simple enough to implement
• Optimize a large fraction of instructions

value (physical register ltlt scale) /- offset
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Optimizer Organization
Computation Simplification
Memory Simplification
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Computation Simplification
RAT CP/RA Table
CP/RA Optimizer Logic
add r3, 1 -gt r6
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Computation Simplification Three Cases
Optimization not possible
Early execution
Dataflow height reduction
add r3, 1 -gt r6
add pr32, 1 -gt pr38
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Memory Simplification
Produced during Computation Simplification
Data Address 0x12345
RLE/SF/ SSR Table
Unknown store address flushes table
RLE/SF/SSR Optimizer Logic
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Optimizing Loads
Optimizing Stores
st r6 -gt 0x12345
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Value Feedback
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Implementation Issues

• Processing dependent instructions

(default no)

• Optimizer latency

(default 2 stages)

• Execution feedback delay

(default 1 cycle)
pipe stages
pipeline stage
add r1, 1, r1
add r1, 1, r1
fetch
optimizer
execute
Xmit delay
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Performance Evaluation

• Experimental Setup
• Alpha ISA
• SPECint, SPECfp, and mediabench
• Pentium 4 style pipeline
• 20 stages minimum for branch resolution
• 22 stages min. with continuous optimizer

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Performance
Average speed up
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Performance Factors

• Dataflow height reduction
• Early instruction execution
• Early branch resolution
• Removal of forwarded loads
• Silent store removal
• Early load address resolution
• Feedback of execution results

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Optimizer Performance
benchmark executed early recovered mispredicted branches load/store address generated loads forwarded silent stores removed
SPECint 32 10 73 13 3
SPECfp 27 29 78 17 3
mediabench 42 20 97 32 3
average 34 20 83 21 3
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Performance Factors
No early load address resolution
No early branch resolution
No early execution
No feedback
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Related Works

• Early load address resolution
• M. Bekerman et al
• Physical register reuse
• S. Jourdan, R. Ronen, and M. Bekerman
• Speculative memory bypassing
• A. Moshovos and G. S. Sohi
• S. Onder and R. Gupta
• G. S. Tyson and T. M. Austin

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Insights

• Primary benefit reduce resource contention and
  absorb data cache miss stalls
• Reduces execution workload -- rebalance
• Certain optimizations are stream-based
• Those requiring only past information
• Single-pass copy propagation

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Summary

• Concept
• Place streaming table-based optimizer in
  processor pipeline
• Benefits
• Dataflow height reduction
• Early branch resolution
• Early instruction execution
• Early load address resolution
• Novel extensions
• Value feedback

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Current Work Alternative Application
Hardware-based trace optimizer

• Upsides
• Off critical path
• Allows dead instrs to be removed
• Downsides
• No value feedback
• No early address resolution, no early execution

Processor Pipeline
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Continuous and Trace Optimization
Preliminary data
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Thanks for your time!

• http//www.crhc.uiuc.edu/bfahs
• ACS http//www.crhc.uiuc.edu/ACS