ANNOUNCEMENTS

1
Lecture 19

• ANNOUNCEMENTS
• Midterm 2 Thursday Nov. 18, 1240-200 pm
• A-L initials in F295 Haas Business School
• M-Z initials in Sibley auditorium
• Closed book, except for an 8.5 x 11 inch sheet of
  notes, calculator OK, no cell phones.
• HW 9 will be due no later than 4 pm Friday Nov.
  12 because of the Veterans Day holiday Nov. 11
• OUTLINE
• The CMOS inverter (contd)
• CMOS logic gates
• The body effect
• Reading (Rabaey et al.)
• Chapter 5.5.1 (p.220 original books pagination)

2
Features of CMOS Digital Circuits

• The output is always connected to VDD or GND in
  steady state
• Full logic swing large noise margins
• Logic levels are not dependent upon the relative
  sizes of the devices (ratioless)
• There is no direct path between VDD and GND in
  steady state
• no static power dissipation

3
The CMOS Inverter Current Flow during Switching
N sat P sat
VOUT
N off P lin
C
V
DD
VDD
S
G
N sat P lin
D
VOUT
VIN
B
D
E
A
D
N lin P sat
G
S
N lin P off
0
VIN
VDD
0
4
Power Dissipation due to Direct-Path Current
VDD
V
DD
vIN
S
G
0
D
i
vOUT
vIN
D
G
i
S
time
5
N-Channel MOSFET Operation
An NMOSFET is a closed switch when the input is
high
A
B
A
B
Y
Y
X
X
Y X if A and B
Y X if A or B
NMOSFETs pass a strong 0 but a weak 1
6
P-Channel MOSFET Operation
A PMOSFET is a closed switch when the input is low
A
B
A
B
Y
Y
X
X
Y X if A and B (A B)
Y X if A or B (AB)
PMOSFETs pass a strong 1 but a weak 0
7
Pull-Down and Pull-Up Devices

• In CMOS logic gates, NMOSFETs are used to connect
  the output to GND, whereas PMOSFETs are used to
  connect the output to VDD.
• An NMOSFET functions as a pull-down device when
  it is turned on (gate voltage VDD)
• A PMOSFET functions as a pull-up device when it
  is turned on (gate voltage GND)

VDD
A1 A2 AN
Pull-up network
PMOSFETs only
input signals

F(A1, A2, , AN)
A1 A2 AN
Pull-down network
NMOSFETs only

8
CMOS NAND Gate
VDD
A B F
0 0 1
0 1 1
1 0 1
1 1 0
A
B
F
A
B
9
CMOS NOR Gate
VDD
A B F
0 0 1
0 1 0
1 0 0
1 1 0
A
B
F
A
B
10
CMOS Pass Gate
A
Y
Y X if A
X
A
11
The Body Effect
VT is a function of VSB
g is the body effect coefficient When the
body-source pn junction is reverse-biased, VT
increases. Usually, we want to minimize g so that
IDsat will be the same for all transistors in a
circuit.
12
Example (0.25mm CMOS technology)