Computer Architecture and Organization

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Computer Architecture and OrganizationMiles
Murdocca and Vincent Heuring
Chapter 10 Advanced Computer Architecture
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Chapter Contents

• 10.1 Parallel Architecture
• 10.2 Superscalar Machines and the PowerPC
• 10.3 VLIW Machines, and the Itanium
• 10.4 Case Study Extensions to the Instruction
  Set The Intel MMX/SSEX and Motorola Altivec
  SIMD Instructions
• 10.5 Programmable Logic Devices and Custom ICs
• 10.6 Unconventional Architectures

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Parallel Speedup and Amdahls Law

• In the context of parallel processing, speedup
  can be computed

Amdahls law, for p processors and a fraction f
of unparallelizable code
For example, if f 10 of the operations must
be performed sequentially, then speedup can be no
greater than 10 regardless of how many processors
are used
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Efficiency and Throughput

• Efficiency is the ratio of speedup to the
  number of processors used. For a speedup of 5.3
  with 10 processors, the efficiency is

Throughput is a measure of how much computation
is achieved over time, and is of special concern
for I/O bound and pipelined applications. For the
case of a four stage pipeline that remains
filled, in which each pipeline stage completes
its task in 10 ns, the average time to complete
an operation is 10 ns even though it takes 40 ns
to execute any one operation. The overall
throughput for this situation is then
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FlynnTaxonomy
Classification of architectures according to
the Flynn taxonomy (a) SISD (b) SIMD (c) MIMD
(d) MISD.
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Network Topologies
Network topologies (a) crossbar (b) bus (c)
ring (d) mesh (e) star (f) tree (g) perfect
shuffle (h) hypercube.
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Crossbar
Internal organization of a crossbar.
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Crosspoint Settings
(a) Crosspoint settings for connections 0 3
and 3 0 (b) adjusted settings to accommodate
connection 1 1.
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Three-Stage Clos Network
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12-Channel Three-Stage Clos Network with n p 6
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12-Channel Three-Stage Clos Network with n p 2
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12-Channel Three-Stage Clos Network with n p 4
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12-Channel Three-Stage Clos Network with n p 3
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C function computes (x2 y2) y2
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Dependency Graph
(a) Control sequence for C program (b)
dependency graph for C program.
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Matrix Multiplication
(a) Problem setup for Ax b (b) equations for
computing the bi.
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Matrix Multiplication Dependency Graph
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The PowerPC 601 Architecture
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128-Bit IA-64 Instruction Word
Each 41 bit instruction consists of three
register addresses (each 7 bits 128 possible
registers), a predicate register (6 bits) and the
opcode and flags or general purpose register (14
bits, varies by instruction).
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Itanium Instruction Types
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Allowable Combinations of IA-64 Instruction Types
Assigned to Instruction Slots
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IA-64 Instruction Issues
Maximum number of IA-64 instructions that can
be executed for each pairing of bundles.
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Intel MMX (MultiMedia eXtensions)
Vector addition of eight bytes by the Intel
PADDB mm0, mm1 instruction
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Intel and Motorola Vector Registers
Intel aliases the floating point registers as
MMX registers. This means that the Pentiums 8
64-bit floating-point registers do double-duty as
MMX registers. Motorola implements 32 128-bit
vector registers as a new set, separate and
distinct from the floating-point registers.
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MMX and AltiVec ArithmeticInstructions
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Comparing Two MMX Byte Vectors for Equality
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Conditional Assignment of an MMX Byte Vector
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A PAL Device
PLAs and PALs are similar except that the OR
gates in a PAL have a fixed number of inputs and
the inputs are not programmable. PALs are more
prevalent than PLAs because they are easier to
manufacture and are less complex.
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Complex Programmable Logic Device
CPLDs are PAL-like or PLA-like blocks that can be
combined with programmable interconnections.
Commercial CPLDs may contain as many as 200,000
equivalent gates and have over 3,000 macrocells.
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Field Programmable Gate Array
Unlike CPLDs, which employ large logic blocks and
fewer interconnection options, FPGAs employ small
logic blocks that can be programmably
interconnected.
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Quantum Computing
Single-particle interference experiment.
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Multi-Valued Logic
Truth tables for binary and ternary comparison
functions
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Neural Networks
Model of a living neuron, and model of an
artificial neuron (below).
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Artificial Neural Network Example
Two simple, feed-forward neural networks with
inputs, weights, and thresholds as shown.