Tunneling Field Effect Transistor

1
Low Power Tunnel FET SRAM Cell Design and Analysis
Jemin Park, Kanghoon Jeon
2
Motivation

• Power limits scaling

• VDD scaling is constrained by VT scaling
  limits

3
Device Design
OFF
LG 30nm
lt N-type TFET gt
ON
lt Band-to-band tunneling gt
4
Current Characteristics of TFET
Reduce VDD
Reduce IOFF
N-type TFET
P-type TFET
NMOSFET
5
TFET SRAM Cell Design
Design I
Design II
Write
Write
Read
Read
6
Comparison with reported data
7
Process Variation (CD, TOX)
?L10nm ?TOX 0.1nm
N-type TFET
P-type TFET
NMOSFET

• ?VT -30mV 15mV

• ?VT -200mV 50mV

8
VT Shift Curve Fitting
NFET
PFET
CD
Tox
9
Systematic(CD,TOX) Random(LER) Variation
CD TOX Variation

• CD 3s15 (4.5nm)
• TOX 3s10 (0.1nm EOT)
• LER s3nm

Total Variation
LER Variation
10
Read/Write SNM Distribution
99.9 12mV
99.9 16mV

• 20(27) variation in SNM falls within 99.9 of
  the distribution
• 8T subthreshold SRAM read margins undergoes a
  70 variation in read SNM with just CD variation

11
SNM Variation with VDD Scaling
16mV_at_VDD 300mV
32.5mV
16mV_at_VDD 300mV
75.1mV
12
Conclusions

• TFET current models were developed and applied to
  SRAM static simulations.
• Two cell designs were proposed and analyzed.
• TFET SRAMs show to be very robust to process
  variations.
• VDD lower than 500mV can be tolerated with
  process variations.