Outline

1
Effects of Global Interconnect Optimizations on
Performance Estimation of Deep Sub-Micron Design
Yu (Kevin) Cao1, Chenming Hu1, Xuejue Huang1,
Andrew B. Kahng2, Sudhakar Muddu3, Dirk
Stroobandt4, Dennis Sylvester5
1EECS Department, University of California,
Berkeley 2Now with ECE and CS Department,
University of California, San Diego 3Formerly
with Silicon Graphics, Inc. 4ELIS Department,
Ghent University, Belgium 5Now with EECS
Department, University of Michigan, Ann Arbor
2
Outline

• Introduction
• Study implementation
• Global interconnect optimization issues
• Inductance effect
• Repeater insertion
• Via parasitics
• Conclusions

3
Performance Prediction

• Performance estimated from critical path analysis
• Previous prediction assumes
• RC line model for interconnect delay
• Switch factor bounded by 0,2
• Optimal repeater sizing and ideal placement
• Design constraints excluded, such as noise
  margin, delay uncertainty and area cost
• Via resistance from buffer insertion neglected
• How valid are these assumptions?

4
Research Framework

• GSRC Technology Extrapolation (GTX) Engine
• http//vlsicad.cs.ucla.edu/GSRC/GTX
• Allows users to flexibly capture and study the
  impact of alternative modeling choices and
  optimization constraints

5
Simulation Setup

• Typical 0.18µm MOSFET technology
• 15mm copper global interconnect, line
  thickness1.3µm
• Inverting buffers inserted

Variables Targets
Line width and spacing Shield configuration Buffer size Buffer placement Line delay Peak noise Delay uncertainty best and worst delay when noise exists
6
Line Inductance

• In DSM regime, inductance is more important with
• Increasing operation frequency
• Lower line resistance
• Larger global interconnect cross-sectional
  dimension
• using Cu

7
Inductance Effect on Line Delay
RC_Bakoglu
225
RLC_Friedman
200
RLC_Kahng/Muddu
175
HSPICE
150
125
Interconnect Delay (ps)
100
75
RLC
-
dominated Case

50
25
3
4
5
6
7
8
9
10
Interconnect Length (mm)

• Line behavior is RLC dominant when b12-4b2lt0,
• where b1RsCRsCLRCL, b2RsC2/6RsRCCL/2RC2/24
  R2CCL/6LCLCL
• Simple RC model underestimates line delay by more
  than 40 in RLC-dominated cases

8
Switch Factor (SF) Effect

• Previous models simply use switch factor bounded
  by 0,2 for further simulations
• Detailed analysis predicts that the range of SF
  can be -1,3, depending on different transition
  time of inputs
• A.B. Kahng, S. Muddu, and E. Sarto, On
  Switch Factor Based Analysis of Coupled RC
  Interconnects, Proc. ACM/IEEE Design Automation
  Conf., June 2000, pp. 79-84

9
Shielding Technology
One Side Shielding (1S)
Two Side Shielding (2S)
No Shielding (NS)
Signal Lines

• Shielding is helpful to define the current return
  path for inductance coupling and to reduce
  crosstalk noise. But it increases area cost for
  signal lines
• Cost function Signal wire pitch x Repeater size
  x Number of repeaters

10
Shielding Cost Optimization

• Cost optimization constraints line delay lt 1ns
  noise peak lt 20 Vdd transition time lt 500ps
  delay uncertainty lt 15
• Ignoring inductance can overestimate cost
  function (gt20)

11
Wire and Repeater Sizing

• For a line with fixed length, its width and
  spacing need to be well sized to optimize delay
• Non-linear dependence of line delay on line
  length enables suitable buffer insertion to
  improve performance
• Buffer scaled based on the loading it drives

12
Wire Size Optimization

• RC formula for optimal line width
  
• RC formula overestimates optimal width up to 30
  from RLC model
• J. Cong and D.Z. Pan, Interconnect
  Estimation and Planning for Deep Submicron
  Designs, Proc. DAC, 1999, pp. 507-510

13
Repeater Size Optimization

• Bakoglu sizing
• Simple sizing expression overestimates optimal
  repeater size by 400

14
Repeater Placement Uncertainty

• Buffers are inserted to specific position to
  optimize delay
• However, repeaters are clustered into blocks to
  minimize wire cost at high level design or
  restricted by available locations
• Parameter e captures this placement uncertainty

Lseg
eLseg
15
Impact of e

• Repeater placement uncertainty e has a large
  impact on peak noise (up to gt70) but little
  impact on delay (lt5)

16
Staggered Insertion of Repeaters

• With inverting buffer, staggered repeater
  placement makes overall switch factor close to
  one
• Peak noise and delay uncertainty benefit from
  staggered insertion
• A. B. Kahng, S. Muddu, and E. Sarto,
  Tuning Strategies for Global Interconnects in
  High-Performance Deep Submicron ICs, VLSI
  Design 10(1), 1999, pp. 21-34

17
Non-staggered vs. Staggered
SF3

• Staggered insertion significantly reduces peak
  noise to 4-7 times smaller than that of normal
  non-staggered insertion and almost eliminates
  delay uncertainty

18
Via Parasitics

• Repeaters are inserted into top-level of metal
  routes
• But devices must be on the bottom substrate
• Current Al technology uses W as via and WNx as
  barrier. Both have larger resistivity than Al

19
Via Resistance Effect

• Total via stack resistance is 47O for 0.18µm Al
  technology (signal line resistance is about
  40O/mm)
• Ignoring via parasitic resistance can introduce
  10-20 underestimation of delay
• In the future copper can be used as via and may
  significantly reduce such impact

20
Summary
Including Delay Noise DU Optimal Size
L
e
Staggered Repeater x x
Rvia x x
previous models underestimate previous
models overestimate x no obvious change
21
Conclusions

• Have quantified several large sources of error in
  standard models used for interconnect
  optimization
• Line inductance, via resistance
• Design techniques shielding, repeater clustering
  and repeater staggering
• Accurate analytical models are required for
  optimal line and repeater sizing, and for
  accurate estimation of interconnect resource
  requirements
• GTX allows rapid development, validation of
  interconnect performance models and optimizations