Michael J' Haney

1
The CLEO-III Trigger Decision and Gating

• Michael J. Haney
• University of Illinois at Urbana-Champaign
• Nuclear Science Symposium and Medical Imaging
  Conference, Lyon, France, October 15-20, 2000
• Paper NSS578
• T.J. Bergfeld2, J.A. Ernst2, G.D. Gollin2, M.J.
  Haney2, R.M. Hans2, E.E. Johnson2,C.L. Plager2,
  C. Sedlack2, M.A. Selen2, and J. Williams2
• 2Department of Physics, University of Illinois at
  Urbana-Champaign, 1110 West Green Street, Urbana,
  Illinois 61801

2
The CLEO-IIItrigger
DR3 preamplifiers
CTL Mixer-Shapers
DAQ
G/CAL
AXX
TILE daughter boards
DFC
AXTR
QVME
DM/CTL
Barrel analog
TIM
Flow control/gating
DM/CTL
TILE daughter boards
Axial drift chamber
QVME
Endcaps analog
STTR
TIM
DM/CTL
TPRO
Stereo drift
SURF
chamber
TPRO
SURF
TIM
CCGL
AXPR
TRCR
L1TR
TIM
DM/CTL
Pulser
LUMI
DM/CTL
Level 1 decision
Calorimeter digital
3
Common Architecture
FPGA based Logic
Inputs
Outputs
Circular Buffer
DAQ/ VME
TDI TMS TCK
TDO
JTAG
4
Interface Boards

• Calorimetry CCGL
• Axial Processor AXPR
• Tracking Correlator TRCR

5
Level 1 TriggerCrate
LUMI
6
The CLEO-IIItrigger
DR3 preamplifiers
CTL Mixer-Shapers
DAQ
G/CAL
AXX
TILE daughter boards
DFC
AXTR
QVME
DM/CTL
Barrel analog
TIM
Flow control/gating
DM/CTL
TILE daughter boards
Axial drift chamber
QVME
Endcaps analog
STTR
TIM
DM/CTL
TPRO
Stereo drift
SURF
chamber
TPRO
SURF
TIM
CCGL
AXPR
TRCR
L1TR
TIM
DM/CTL
Pulser
LUMI
DM/CTL
Level 1 decision
Calorimeter digital
7
L1 Trigger Board
8
L1 Trigger Implementation
9
L1 TriggerImplementation
10
L1 TriggerDefinitions

• Generic Hadron Line, Barrel Timing
• SUBDESIGN line0(
• in117..0 INPUT
• out OUTPUT
• )
• Variable
• 1cblow SOFT
• 3tracks SOFT
• evtime SOFT
• Begin
• -- trigger bit mappings
• tr_time1..0 in1..0
• cb_time1..0 in3..2
• ce_time1..0 in5..4
• cc_time1..0 in7..6
• tr_n_hi3..0 in11..8
• tr_n_lo3..0 in15..12

11
Luminosity LUMI
LumiLogic
Scalers
SURF
179TRIGbits
QPR
VMEinterface
DFC
L1 Pass
Backplane
12
The CLEO-IIItrigger
DR3 preamplifiers
CTL Mixer-Shapers
DAQ
G/CAL
AXX
TILE daughter boards
DFC
AXTR
QVME
DM/CTL
Barrel analog
TIM
Flow control/gating
DM/CTL
TILE daughter boards
Axial drift chamber
QVME
Endcaps analog
STTR
TIM
DM/CTL
TPRO
Stereo drift
SURF
chamber
TPRO
SURF
TIM
CCGL
AXPR
TRCR
L1TR
TIM
DM/CTL
Pulser
LUMI
DM/CTL
Level 1 decision
Calorimeter digital
13
Data Flow Control DFC

• accepts L1Pass from LUMI
• produces L1Accept L1Pass Busy
• Busy (and Error) from DAQ crates
• self-Busy to rate limit trigger to 1 kHz
• overflow Busy if DM/CTL does not readout event
  time
• produces CAL
• calibration pulse (from VME register)
• programmable delay, then L1Accept

14
Data Flow Control DFC

• programmable delay and width
• for L1Accept
• for CAL
• produces Synch
• once every 256 L1Accepts
• DAQ crates count event numbers, expect Synch
• Error if missing, or at wrong time
• L2Data and L2Strobe
• for later use

15
Data Flow Control DFC

• detailed bookkeeping
• event numbers, times (42 ns precision)
• total L1Passes
• total_L1 - event_num suppressed triggers
• total, current, and max Busy
• total, current, and max Error

16
Data Flow Control DFC

• single 6Ux160mm VME board
• 4 FPGAs
• VME interface
• L1Pass/Accept, and bookkeeping
• identical Busy and Error bookkeeping FPGAs
• TTL for logicPECL for timing
• unused backplane lines for connection to GCAL(s)

17
Gating and Calibration GCAL

• distributes L1Accept and CAL from DFC
• programmable delay and width
• 42 ns precision, 1.4 ms range
• accepts Busy and Error from DAQ subsystems
• also distributes 42 ns clock (optional)and
  L2Data and L2Strobe (later)

18
Gating and Calibration GCAL

• 6Ux160mm
• up to 18 boards in one subrack
• each GCAL services two DAQ crates
• LVDS communications to DAQ
• TTL for logicPECL for timing

19
Gating and Calibration GCAL