Computer Science 222

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Computer Science 222
Chapter 3.5.1 THE PENTIUM II
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The Pentium II
The Pentium II is a direct descendant of the 8088
CPU used in the original IBM PC. Although the
Pentium II with its 7.5 million transistors is a
far cry from the 29,000-transistor 8088, it is
fully backward compatible with the 8088 and can
run unmodified 8088 binary programs (not to
mention programs for all the intermediate
processors as well).
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The Pentium II
From a software point of view, the Pentium II is
a full 32-bit machine. It has the same
user-level ISA as the 80386, 80486, Pentium, and
Pentium Pro, including the same registers, same
instructions, and a full on-chip implementation
of the IEEE 754 floating-point standard. From a
hardware perspective, Pentium II is something
more since it can address 64 GB of physical
memory and can transfer data to and from memory
in units of 64 bits.
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The Pentium II
Although the programmer cannot observe these
64-bit transfers, they do make the machine faster
than a pure 32-bit machine would be. Internally,
at the microarchitecture level, the Pentium II is
basically a Pentium Pro with the MMX instructions
added. ISA level instructions are fetched from
memory way in advance and are broken up into
RISC-like micro-operations.
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The Pentium II
These micro-operations are stored in a buffer,
and as soon as one of them has the necessary
resources to execute, it can be started.
Multiple micro-operations can be started in the
same cycle, making the Pentium II a superscalar
machine. The Pentium II has a two-level cache.
There are a pair of on-chip caches, 16 KB for
instructions and 16 KB for data, as well as a
512-KB unified second-level cache.
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The Pentium II
The cache line size is 32 bytes. The second
level cache runs at half the clock frequency of
the CPU. CPU clocks are available at 233 MHz and
up.
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The Pentium II
Two primary external buses are used in Pentium II
systems, both of them synchronous. The memory
bus is used to access the main DRAM the PCI bus
is used for talking to I/O devices. Sometimes a
legacy (i.e., ancient) bus is attached to the PCI
bus to allow old peripheral devices to be plugged
in.
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The Pentium II
A Pentium II system can have either one or two
CPUs that share a common memory. On a two-CPU
system, there is the danger that if a word is
read into one cache and modified there without
being written back to memory, if the other CPU
tries to read the word, it will get an incorrect
value. Special support (snooping) is provided to
prevent this problem.
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The Pentium II
One substantial difference between the Pentium II
and all of its predecessors is its packaging.
From the 8088 up through and including the
Pentium Pro, all Intel CPUs were normal chips,
with pins on the side or bottom that could be
plugged into sockets. In contrast, the Pentium II
comes in what Intel calls an SEC (Single Edge
Cartridge).
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As can be seen above, an SEC is a fairly large
plastic box containing the CPU, level 2 cache,
and an edge connector for exporting the signals.
The Pentium II SEC has 242 connectors.
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The Pentium II
While Intel no doubt had good reasons for going
to this packaging model, it produced a problem in
a dimension Intel did not anticipate. Apparently
many customers are in the habit of unscrewing
their computers to look for the CPU chip. On the
first Pentium Its shipped, the customers could
not find the CPU and complained loudly ("My
computer does not have a CPU in it!").
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The Pentium II
Intel solved this problem by pasting a picture of
the CPU chip (actually, a hologram) on the front
of all subsequent SECs shipped.
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The Pentium II
Power management is a major issue for the Pentium
II. The amount of heat given off depends on the
clock frequency, but it is in the range of 30 -
50 watts. That is an enormous amount for a
computer chip. To get some idea of what 50 watts
feels like, put your hand near (but not on) a
50-watt light bulb that has been on for some
time.
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The Pentium II
Consequently, the SEC is outfitted to accept a
heatsink, which is required to dissipate the heat
generated. This property means that when a
Pentium II has outlived its usefulness as a CPU,
it can always be used as a camp stove.
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Pentium II Camp Stove
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The Pentium II
According to the laws of physics, anything that
puts out a lot of heat must suck in a lot of
energy. In a portable computer with a limited
battery charge, using a lot of energy is not
desirable. To address this issue, Intel has
provided a way to put the CPU to sleep when it is
idle and to put it into a deep sleep when it is
likely to be that way for a while.
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The Pentium II
When in deep sleep state, the cache and register
values are preserved, but the clock and all the
internal units are turned off. It is not known
whether a Pentium II can dream when it is in deep
sleep.
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The Pentium II's Logical Pinout
The 242-edge connectors on the SEC are used for
170 signals, 27 power connections (at several
different voltages), 35 grounds, and 10 spares
for future use. Some of the logical signals use
two or more pins (such as the memory address
requested), so there are only 53 different ones.
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A somewhat simplified logical pinout is given in
here. On the left side of the figure are the six
major groups of memory bus signals on the right
side are various miscellaneous signals.
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The names given entirely in upper case are the
actual Intel signal names. The ones given in
mixed case are collective names for multiple
related signals.
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Intel uses a naming convention that is important
to understand. Because all chips are designed
using computers these days, there is a need to be
able to represent signal names as ASCII text.
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Using overbars to indicate signals that are
asserted low is too difficult, so Intel puts the
symbol after the name instead. Thus BPRI is
expressed as BPRI.
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As can be seen from the figure, most Pentium II
signals are asserted low.
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The first group of signals is used to request the
bus (i.e., do bus arbitration). BPRI allows a
device to make a high priority request, which
takes precedence over a regular one.
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LOCK allows a CPU to lock the bus, to prevent
the other one from getting in until it is
done. Once bus ownership has been acquired, a CPU
or other bus master can make a bus request using
the next group of signals.
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Addresses are 36 bits, but the loworder 3 bits
must always be 0 and therefore do not have pins
assigned, so A has only 33 pins. All transfers
are 8 bytes.
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With 36 address bits, the maximum addressable
memory is 236 which is 64 GB.
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When an address is put onto the bus, the ADS
signal is asserted to tell the target (e.g., the
memory) that the address lines are valid.
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The type of bus cycle (e.g., read one word or
write a block) goes on the REQ lines. Two of
the parity signals protect A and one protects
ADS and REQ.
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The five error lines are used by the slave to
report parity errors and by all devices to report
certain other errors.
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The Snoop group is used in multiprocessor systems
to allow one CPU to find out if a word it needs
is in the other CPU's cache.
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The Response group contains signals used by the
slave to report back to the master. RS contains
the status code. TRDY indicates that the slave
(the target) is ready to accept data from the
master.
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These signals are also parity checked.
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The last bus group is for the actual data
transfer. D is used to put 8 data bytes onto
the bus. When they are placed there, DRDY is
asserted to announce their presence.
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DBSY is used to tell the world that the bus is
currently busy.
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RESET is used to reset the CPU in the event of a
calamity.
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The Pentium II can be configured to use the
interrupts the same way as on the 8088 or it can
also use a new interrupt system using a device
called an APIC (Advanced Programmable Interrupt
Controller).
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The Pentium II can run at any one of several
voltages, but it has to know which. The VID
signals are used for automatic power supply
voltage selection.
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The Compatibility signals are used to fool
ancient devices on the bus that think they are
talking to an 8088.
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The Diagnostics group contains signals for
testing and debugging systems in conformance with
the IEEE 1149.1 JTAG test standard.
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The Initialization group deals with booting
(starting) the system.
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The Power management group allows the CPU to be
put into sleep state and deep sleep state.
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Finally, the miscellaneous group is a hodge-podge
of signals including one that is asserted by the
CPU if the internal temperature of the CPU ever
reaches 130C (266F).
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If a CPU ever hits this temperature, it is
probably dreaming about retirement and becoming a
camp stove.
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Pipelining on the Pentium II's Memory Bus
Modern CPUs like the Pentium II are much faster
than modern DRAM memories. To keep the CPU from
starving for lack of data, it is essential to get
the maximum possible throughput from the memory.
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Pipelining on the Pentium II's Memory Bus
For this reason, the Pentium II memory bus is
highly pipelined, with as many as eight bus
transactions going on at the same time. We saw
the concept of pipelining in Chap. 2 in the
context of a pipelined CPU, but memories can also
be pipelined.
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Pipelining on the Pentium II's Memory Bus
To allow pipelining, Pentium II memory requests,
called transactions, have six stages   1. The
bus arbitration phase. 2. The request phase. 3.
The error reporting phase. 4. The snoop phase. 5.
The response phase. 6. The data phase.
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1. The bus arbitration phase.
Not all phases are needed on all transactions.
The bus arbitration phase determines which of
the potential bus masters goes next.
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2. The request phase.
The request phase allows the address to be put
onto the bus and the request made.
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3. The error reporting phase.
The error reporting phase allows the slave to
announce that the address had a parity error or
that something else is wrong.
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4. The snoop phase.
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4. The snoop phase.
The snoop phase allows one CPU to snoop on the
other one, something only needed in a
multiprocessor system.
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5. The response phase.
The response phase is where the master learns
about whether it is about to get the data it
wants.
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6. The data phase.
Finally, the data phase allows the data to be
sent back.
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The secret to the Pentium II's pipelined memory
bus is that each phase uses different bus
signals, so that each one is completely
independent of the other ones.
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The six groups of signals needed are the ones
shown on the left. For example, one CPU can try
to get the bus using the arbitration signals.
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Once it has acquired the right to go next, it
releases these bus lines and starts using the
Request group's lines.
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Meanwhile, the other CPU or some I/O device can
enter the bus arbitration phase, and so on.
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The figure above shows how multiple bus
transactions can be outstanding at the same time.
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The bus arbitration phase is not shown because it
is not always needed. For example, if the
current bus owner (often the CPU) wants to run
another transaction, it does not have to
reacquire the bus. It only has to ask for the
bus again after it passes bus ownership to
another requesting device.
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Transactions 1 and 2 are straightforward five
phases in five bus cycles.
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Transaction 3 introduces a longer data phase, for
example, because it is a block transfer or
because the memory addressed inserted a wait
state.
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As a consequence, transaction 4 cannot start its
data phase when it would like to. It observes
that the DBSY signal is still asserted and just
waits for it to be negated.
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In transaction 5 we see that the response phase
can also take multiple bus cycles, thus delaying
transaction 6.
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Finally, in transaction 7, we notice that once a
bubble has been introduced into the pipeline it
remains there if new transactions keep starting
consecutively.
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In actual practice, however, it is unlikely that
the CPU will attempt to start a new transaction
on every single bus cycle, so bubbles do not last
so long.
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