64Bit AND Gate

1
64-Bit AND Gate

• Phong Nguyen
• Steve Turner
• Harpreet Dhillon
• Mahrang Saeed
• Advisor Dave Parent
• 5/8/06

2
Agenda

• Abstract
• Introduction
• What we learned
• What its used for
• Theory
• Project Summary
• Project Details
• Results
• Time schedule
• Conclusions

3
Abstract

• Designed a 64 bit AND gate that operates at 400
  MHz and occupies an area of 807x320um2.

4
Introduction

• By doing this project, we learned how to do a
  full custom IC design.
• 64-bit AND gate is useful in doing 64-bit
  processing.

5
Project Summary

• 400 Mhz 64 bit and gate
• 3.65 error between worst case and best case
  input vectors
• Tplh equals 2.1ns and Tphl equals 1.57ns
• Power 2.35 mW _at_ 400 MHz
• Power 1.17 mW _at_ 200 MHz

6
Longest Path Calculations
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Schematic with worst case path
blackcell flip-flop x 64 redcell 8bit cell x
8 bluecell last 8bit cell
8
Final Layout
9
Verification
10
NCVerilog
only time when all bits are 1, output is 1
11
Transient Simulation tphl
12
Transient Simulation tplh
13
Time Schedule
14
Lessons Learned

• Before starting layout spend time on making a
  floor plan
• Using Cell based design makes it easy It
  reduces debug time
• Time management is the main key to complete any
  project
• Also pay attention to best case delay as well
• See professor more often, keep updated

15
Summary

• It can be used for 64 Bit Processing
• Max. Frequency - 400 Mhz
• Error between worst and best case input vectors
  is only 3.65
• Tplh equals 2.1ns and Tphl equals 1.57ns
• Power 2.35 mW _at_ 400 MHz
• It can be used in a bigger project

16
Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Professor Parent for his time
  guidance