A LowPower OOK Digital Transceiver

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A Low-Power OOK Digital Transceiver

• Neil MacEwen
• University of Strathclyde
• Neil.macewen_at_eee.strath.ac.uk

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Summary

• Design issues for motivating example
• Building a simple test system
• Implementation details
• Future issues

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A Motivating Example

• Demonstrate Specknet capabilities
• Simple application
• Finite number of Specks with simple processing
  and communication abilities
• Targeted volume of 5mm3
• Current battery technology at that size results
  in very strict power budget
• A test digital radio transceiver must be designed
  with this as first priority

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The RF point of view

• Most power-hungry element of Speck
• Limit at all times power-intensive components
• On-Off-Keying (OOK) modulation
• Envelope detector
• Removes layer of synchronisation from digital
  receiver

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Receiver Synchronisation

• Several levels of synchronisation
• Envelope detector makes carrier synchronisation
  redundant

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Receiver Synchronisation

• Ideally take one sample per symbol
• Simplify things by oversampling
• Early/late gate synchronisation

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Simplifying Symbol Synchronisation

• Assume bandwidth is not limited
• Further simplification achievable by encoding the
  transmitter clock within the data
• Manchester encoding
• XOR bit stream with the clock
• 1 gt clock pulse
• 0 gt 180 phase shifted clock pulse
• Transition within every bit period used for
  synchronisation

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Manchester Encoding

• Manchester encoded waveform
• Long strings of ones or zeros no longer exist
• Nearly twice the bandwidth

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A Simple Test System

• Test system implemented on Nallatech Xtreme DSP
  development kit (Xilinx Virtex-II 2V3000)

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Manchester Decoder

• Simple structure consisting of a transition
  detector and a counter
• Counter is used to avoid detecting invalid
  transitions

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Manchester Decoder
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Packet Format

• Packet format extremely simple
• Needs some consideration
• Preamble and Start of Frame Delimiter (SFD) used
  for frame synchronisation / system start-up
• Cyclic Redundancy Check (CRC)

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FPGA Implementation

• Equivalent gate count of 18,845
• Very rough number Louise will cover in more
  detail

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Future issues

• MAC, error checking, addressing, sleep mode,
  RSSI, AGC, test over RF link

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Review

• Design issues for simple transceiver
• Manchester-encoded test system has been
  implemented
• Next steps