Timing Recovery Unit for a 1'6 Mbps DSSS Receiver

1
Timing Recovery Unit for a 1.6 Mbps DSSS Receiver
2
Problem Statement

• Design a 1.6 Mbps DSSS timing recovery unit
• Modulation
• Length 31 PN code
• QPSK symbol constellation
• System specifications
• Maximum frequency offset of /- 200 KHz
• Maximum timing offset of /- 20 KHz
• Minimum input SNR of 5 dB
• Input is in-phase quadrature samples at 200 MHz
  with 7 bits each
• Primary design criterion is power minimization
• Implementation using SSHAFT design flow
• Datapath blocks designed in Simulink, implemented
  in Module Compiler, verified through VHDL
  simulations
• Control designed in Stateflow
• Datapath and Control composed in Simulink

3
Algorithm

• Input 8 pre-interpolated data streams from ADC
• Coarse timing and code acquisition
• feedforward, non-data-aided algorithm based on a
  matched filter
• Joint carrier offset and fine timing
• feedforward and data-aided synthesized directly
  from ML equations
• Sample time tracking using early/late correlator
• Phase estimation using phase-locked loop (PLL)
• Data-aided acquisition using known pilot symbols
  to estimate phase offset
• Decision-directed data reception using detected
  symbols to calculate error

4
Implementation Highlights

• Data flow blocks written in Module Compiler
  (Synopsys) synthesized to VHDL
• Control written in StateFlow synthesized to VHDL
• Blocks assembled in Simulink with 5 gated clock
  domains
• Tapeout using SSHAFT hierarchical assembly
• Extensive block reuse enabled by parameterized
  modules
• CORDIC slice instantiated 27 times
• Multiply-accumulate instantiated 12 times

5
PLL
Single symbol time execution required to
implement loop transfer function
6
PLL Verification
PLL Input Symbols PLL Soft Output Symbols
Phase Error Phase Correction
First pilot symbol to PLL
PLL locked when error within 0.1 radians
First data symbol to PLL
First data symbol out of PLL!!
7
Flat vs. Hierarchical

• Hierarchical takes longer to floorplan
• Hierarchical passes through flow faster
  (especially routing)
• Hierarchical produces fewer LVS and DRC errors
  (probably due to router doing better on smaller
  blocks)
• Hierarchical produces similar areas (with careful
  floorplan)
• Will use hierarchical for final design

8
TCIR Receiver Digital Baseband Preliminary Netlist
Same netlistRouted Hierarchically Routed Flat
1.30 mm
1.06 mm
0.85 mm
1.07 mm
Area 1.134 mm2
Area 1.105 mm2
9
External Interfaces

• Three external interfaces required
• Stream interpolation and decimation
• Produce 8 evenly spaced 25 MHz streams from 100
  MHz data
• Register Read/Write Interface
• Program spreading codes and other configuration
• Physical to Protocol Interface (PPI)
• Receive control from and send data to protocol
  chip
• Core VDD 1V, Pad VDD 1.8V, on-chip level
  shifters for conversion

10
Status and Results

• Tapeout Summer 2001
• Nominal clock rate is 25 MHz
• Estimated power consumption
• Carrier search mode 7.6 mW
• Acquisition mode 0.47 mW
• Data reception 1 mW

Chip floorplanestimated die area 1.5 mm2