Ion Mandoiu

1
Challenges in Design
Automation for Nanoscale VLSI DNA Systems

• Ion Mandoiu
• ECE Department, UC San Diego

2
Outline

• Challenges for nanoscale VLSI and DNA systems
• New framework for VLSI interconnect synthesis
  optimization
• Probe placement algorithms for DNA arrays
• Future research directions

3
VLSI Historical Integration Trends
Source Intel
4
Will these trends continue?

• Moore ISSCC03 No exponential is forever but
  we can delay forever

5
Will these trends continue?

• Moore ISSCC03 No exponential is forever but
  we can delay forever

• International Technology Roadmap for
  Semiconductors (ITRS)
• 800 experts from industry, academia, governments
  worldwide
• Sets RD targets for all semiconductor supplier
  industries lithography, interconnect, process
  integration, design, test, packaging,

• Exponential integration rate targeted to continue
  for gt15 years
• Current (2001) roadmap targets (http//public.itrs
  .net)
• Physical gate length 65nm in 2001 ? 9nm by 2016
• Transistors / cm2 184 million in 2001 ? 7.2
  billion by 2016

6
Nanoscale VLSI Design Challenges

• Nanoscale design challenged by
• System complexity
• New dominant physical effects

• ? Timing
• - Faster gates, slower wires
• ? Signal integrity
• - Closer wires ?increased coupling noise,
  crosstalk
• Power consumption
• - Increased power density, leakage
• ? Manufacturing reliability
• - Non-scaling defect density and process variation

• ? Verification and test
• Exploding of test vectors

7
DNA Arrays

• DNA arrays
• Short DNA probes bound to a glass substrate
• Detect matching single-strand DNA molecules

• Growing number of applications
• Diagnosis of genetically based conditions
• Point of care diagnosis (low-cost, real-time)
• Targeted treatment
• E.g., antibiotic sensitivity
• Drug discovery
• Sequencing, genotyping, gene expression
  monitoring
• Agricultural research, environmental impact,
  bio-warfare agents,

8
VLSI-like Manufacturing Process

• Very Large Scale Imobilized Polymer Synthesis
  (VLSIPS)
• Light-directed combinatorial chemical synthesis

9
Scaling Trends and Challenges

• Smaller is better for DNA arrays
• Reduced reagent consumption
• Higher reaction speed
• Higher parallelism

• but brings challenging system complexity new
  dominant physical effects
• ½ million probes / array ? 100 million probes /
  next generation array
• Unwanted illumination caused by light diffraction
• ? Emerging DNA array design automation field
• Need scalable design tools, mature methodologies
• Great potential for transfer of techniques and
  methodologies from VLSI design automation

10
New Framework for VLSI Global Interconnect
Synthesis and Optimization
ASP-DAC02 Best Paper

• Joint work with
• C. Albrecht (Synopsys)
• A.B. Kahng (UCSD)
• A. Zelikovsky (GSU)

11
Interconnect Scaling Trends
Global interconnect gets slower
Repeaters help
Local interconnect gates get faster
12
Global Interconnect Optimizations
13
Buffered Global Routing Problem

• Degrees of freedom
• Route selection
• Buffer locations/sizes
• Pin assignment,
• Constraints
• Buffer load
• Timing
• Routing congestion,
• Objectives
• Wirelength
• buffers,

14
Tile Graph Congestion Model
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Buffered Global Routing Formulation

• Given
• Tile graph G with
• wire capacity w(u,v) routing channels
  between tile u and v
• buffer capacity b(v) buffers sites in
  tile v
• Netlist (decomposed into 2-pin nets)
• Maximum buffer load U (in tiles)

Find Feasible buffered routing minimizing
?(buffers) ?(total wirelength)
Integer multicommodity flow RaghavanT87,,Albrech
t01
16
Buffered Global Routing Formulation

• Given
• Tile graph G with
• wire capacity w(u,v) routing channels
  between tile u and v
• buffer capacity b(v) buffers sites in
  tile v
• Netlist (decomposed into 2-pin nets)
• Maximum buffer load U ( of tiles)

Find Feasible buffered routing minimizing
?(buffers) ?(total wirelength)
Multicommodity flow formulation for buffered
version?
17
Gadget for Load Constraints
18
Gadget for Load Constraints
Constant factor increase in size of grid graph
19
Further Extensions

• Similar gadgets capture
• Minimum buffer load constraints
• Pin assignment
• - Buffer sizing
• - Wire sizing
• - Layer assignment
• Sink delay upper bounds (Elmore-Delay)

20
Integer Program
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21
Randomized Rounding Approach

• Solve fractional relaxation, then round variables
  with probability given by fractional values
• Provably good solution quality RaghavanT87
• Previous exact and approximation algorithms for
  solving the fractional relaxation too slow in
  practice

• Key contribution fast approximation algorithm
  for solving the fractional relaxation
• Generalizes approximate multicommodity flow
  algorithms of GargK98, Fleischer99 to
  separable packing linear programs (set capacity
  constraints)

22
High-Level Algorithm

• Iteratively construct both primal and dual
  solutions
• Route flow along min-weight paths w.r.t. dual
  variables
• Main subroutine Dijkstras shortest path
  algorithm
• For every path, update dual variables by
  multiplying with a small factor gt 1

THEOREM Factor (1?) approximation for MCF
fractional solution with O(?-2 k log(n))
shortest-path computations k nets, n
graph nodes
23
Experimental Results

• Compared algorithms
• RABID algorithm of Alpert et al. (DAC01 best
  paper award)
• MCF multicommodity flow based algorithm
• MCFPA multicommodity flow based algorithm with
  integrated pin assignment
• Grid size 30x30
• Buffer load upper-bound 6-7 tiles
• Circuits with up to 2,100 nets and up to 37,000
  buffer sites

24
Experimental Results
25
Experimental Results
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Summary

• Powerful algorithmic framework
• Simultaneous optimization of wire routes, buffer
  locations and sizes, pin layer assignments,
  under given congestion and timing constraints
• Powerful tool for design-space exploration, e.g.,
  accurate computation of the area-congestion
  tradeoff curve during floorplan evaluation
• Predictable runtime and solution quality
  flexible tradeoff

• Ongoing work
• Further improvements in algorithm scalability
• Faster dual update rules
• Sub-quadratic dependence on inverse of accuracy?
• Uneven tile sizes, window vs. tile buffer
  constraints

27
Probe Placement Algorithms for DNA Arrays
WABI02 RECOMB03

• Joint work with
• A.B. Kahng (UCSD)
• P. Pevzner (UCSD)
• S. Reda (UCSD)
• A. Zelikovsky (GSU)

28
Unwanted Illumination Effect

• Unwanted illumination ? erroneous probes
• Effect gets worse with technology scaling

29
Example Probe Synthesis
30
Example Probe Synthesis
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Example Probe Synthesis
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Measure of Unwanted Illumination
Unwanted illumination ? border length
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Synchronous Synthesis

• Periodic deposition sequence, e.g., (ACTG)k

? border conflicts b/w adjacent probes 2 x
Hamming distance
34
2D Placement Problem
Edge cost 2 x Hamming distance
35
Previous Approaches

• Hubbell 90s
• Find TSP w.r.t. Hamming dist
• Thread TSP to grid row by row

• TSP-based methods do not scale to gt 106 probes
• ? Transfer scalable techniques from VLSI
  placement!

36
2D Placement Sliding-Window Matching

• Slide window over entire chip
• Repeat until improvement drops below certain
  threshold

37
Effect of Window Size
38
2D Placement Epitaxial Growth

• Simulates crystal growth

• O(N3/2) row-order implementation, where N
  probes

39
Asynchronous Synthesis

• Probes grow at different speeds
• border conflicts b/w adjacent probes depends on
  their embedding into the nucleotide deposition
  sequence

? 3D placement problem
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Single-Probe Embedding

• Dynamic programming algorithm similar to LCS

41
Post-Placement Embedding Optimization

• 2D placement fixed, allow only probe embeddings
  to change

• Greedy optimally re-embed probe with largest
  gain
• Chessboard Algorithm alternate re-embedding of
  red and green probes

42

Embedding Optimization Results

• Chessboard is 5-6 better than greedy
• Within 21 of lower-bound

43

Comparison of Placement Algorithms
Chip size 100x100 to 500x500

• SWM 600x faster (5 min. vs. 30 hours) with up to
  4 border conflict decrease
• 20 Row-Epitaxial 6-10 better than
  TSPThreading, gt10x faster for 500x500

44
Summary

• Results demonstrate effectiveness of VLSI
  placement techniques to DNA probe placement
• Currently exploring other VLSI placement
  techniques, e.g., recursive 4-way partition based
  on linear-time clustering methods

• Algorithms validated on industry data
• Extended to handle practical constraints such as
  control probes, match/mismatch probe pairs
• 5 border length improvement over industry
  placements
• ? Improved design results in fewer erroneous
  probes, smaller array area, and/or more probes
  per array

45
Research Directions

• Approximation Algorithms
• Network design, routing, wireless networks,
  auctions,
• VLSI
• Physical design (non-Manhattan interconnect
  architectures, clock synthesis)
• Design for test (built-in self-test)
• Design for manufacturing reliability (redundant
  interconnect)
• DNA
• Enhanced design flow (flow-aware optimizations,
  feedback loops)
• Manufacturing cost optimization (multi-project
  wafers)
• VLSIDNA
• Lab-on-a-chip