Rochester DPP project

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Digital Pulse Processor DDC-8 (Universal Trigger
Module) for PHOBOS.
Wojtek Skulski University of Rochester
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Outline

• Trigger application in PHOBOS.
• Description of the Universal Trigger Module
  DDC-8.
• Two configurations
• 1. Standalone module without DAQ readout.
• 2. VME front-end with DAQ readout.
• Response to scintillator pulses.
• Programming tools
• FPGA programming tools.
• Embedded microprocessor tools.
• PC GUI programming environment.

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Online trigger

• Analog signals Paddles, Cerenkov, ZDC.
• Logic signals from conventional NIM.
• 1st level processing DDC.
• 2nd level processing XLM, optional.
• Accept/reject event within about 1 msec.

PHOBOS _at_ RHIC
Centrality from paddle and ZDC.
Vertex definition from TACs. T0 OR Dt, Paddle
Dt, ZDC Dt.
Vertex and centrality definition in real time
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Possible configurations

• Standalone Universal Trigger Module DDC-8.
• 8 flash ADC channels 41 logic I/O.
• Standalone data acquisition and histogramming.
• Counting House interfaces USB and JTAG.
• Tunnel interface RS-232.
• Real-time decision fast.
• DAQ readout no.
• The combo system UTMXLM.
• 8, 16, 24, or 32 flash ADC channels many logic
  I/Os.
• Real-time decision slower due to additional
  layer.
• DAQ readout yes.
• More complicated programming.

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DDC-8
JTAG connector
ADC 40 MHz 10 bits (8 channels)
RAM 500 kB
Analog signal IN 8 channels with digital
offset and gain control
micro processor
RS-232
USB
ECL clock IN (optional)
FPGA
Signal OUT 40 MHz 10 bits
Logic connectors NIM 16 lines IN, 8 lines OUT
16 bidirectional TTL lines 1 in (fast parallel
interface to XLM)
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Single channel 12-bit prototype, development and
testing

• Input channel for waveform capture, up to 65
  Msamples/s.
• Output reconstruction channel for development and
  diagnostic.
• The channel design to be used for the 12-bit
  multichannel board.

JTAG connector
ADC 65 MHz 12 bits
Variable gain amp
FPGA
Signal IN
USB processor connector
Signal OUT
Fast reconstruction DAC 65 MHz 12 bits
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One flash ADC channel, DDC-x
Clock
Gain and offset control
Pulse height and shape
ASC
Nyquist filter
ADC
Sample rate processor
Event rate processor
Signal from preamplifier
Waveform memory
Legend ASC Analog Signal Conditioning ADC
Analog to Digital Converter
Optional external trigger
Trigger
Individual trigger
analog
digital
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Front end block diagram, DDC-8
16NIM in
8NIM out
17TTL in/out
Analog section
Digital section
Channel 1
Correlation processor
User-defined 17 I/O lines OR parallel interface
...
Analog section
Digital section
Channel 2
Analog section
Digital section
Channel 8
Analog section
Digital section
Channel OUT
Composite internal trigger
Internal triggers from channels 18
Optional external trigger (one of the 16 NIM in
lines)
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Composite configuration UTMXLM
1, 2, 3, or 4 UTM modules one XLM
Flash ADC front end
32 flash ADCs
XLM-72 900 MFLOPs 4 MB 40,000 gates
DAQ
8 chan
64NIM in
32NIM out
8 chan
1.2 million gates in the FPGAs
8 chan
VME
On-the-fly data preprocessing
8 chan
On-board monitoring
Four independent parallel interfaces, 100 MB/s.
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DDC-8 features
of analog input channels 8. of
analog output channels 1. of logic
inputs NIM 16. of logic
outputs NIM 8. of in/out
lines TTL 161. Fast interfaces
USB, parallel. Slow interfaces
RS-232, SPI, I2C. Waveform memory
12 msec. On-board microprocessor 8 bits,
10 MIPS. Histogramming memory 0.5
MB. Packaging NIM,
standalone. Intermediate scale
SuperBallDwarfBall. Medium scale PHOBOS
trigger. Small scale table-top DPP
systems, student research
projects, DPP algorithm
development.
Features
Applications
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Response to scintillation pulses

• DDC-8 firmware is under development.
• Results obtained with DDC-1, 48 MHz _at_ 12 bits.
• Very fast plastic BC-404 tpulse lt tsampling.
• NaI(Tl) tpulse gt tsampling.
• CsI(Tl) particle identification.
• Phoswich two-component FAST-SLOW pulses.

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Response to scintillator pulses fast plastic
scintillator A typical pulse in PHOBOS environment
Signal from a Bicron BC-404 detector digitized
with the 1-channel prototype at 48 Msamples/s
12 bits Reliable digitization thanks to the
antialiasing filter.
Excellent response to a very fast pulse
Tek screen for reference
1 sample 20.8 ns
1 sample 0.2 ns
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Signal from a phoswich detector digitized with
the DDC-1 48 Msamples/s at 12 bits
cosmic ray
FAST clearly separated from SLOW
CsI(Tl) crystal
SLOW
Bicron BC-404
FAST
phototube
1 sample 20.8 ns
teflon
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Medium-fast scintillator pulses NaI(Tl)
Signals from a Bicron 2x2 NaI(Tl)
detector digitized with the 1-channel prototype
at 48 Msamples/s 12 bits
137Cs
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Response to scintillator pulses CsI(Tl)
g-ray 1 cm3 CsI(Tl) phototube
1-channel prototype at 48 Msamples/s 12
bits Note pulse shape dependence on type
of radiation. a-particle
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Particle ID from CsI(Tl)
Traditional slow-tail representation 1 cm3
CsI(Tl) phototube 1-channel prototype
at 48 Msamples/s 12 bits natTh radioactive
source PID TAIL / TOTAL Note
energy-independent PID
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Research application SuperBall DwarfBall
4p charged particle detector DwarfBall/DwarfWall.
PlasticCsI(Tl) phoswich detectors.

• Online pulse shape analysis with DDC.
• Charged particle ID with CsI(Tl)/plastic.
• Neutron capture counting and timing.
• 1st level processing DDC.
• 2nd level processing XLM.

Neutron Calorimeter SuperBall. 16 m3 organic
liquid scintillator.
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Online trigger

• Analog signals Paddles, Cerenkov, ZDC.
• Logic signals from conventional NIM.
• 1st level processing DDC.
• 2nd level processing XLM, optional.
• Accept/reject event within about 1 msec.

PHOBOS _at_ RHIC
Centrality from paddle and ZDC.
Vertex definition from TACs. T0 OR Dt, Paddle
Dt, ZDC Dt.
Vertex and centrality definition in real time
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How fast can we digitize the pulse?
Signal from a pocket NIM pulser digitized with
the DDC-8 at 40 Msamples/s 10 bits Excellent
response to a very fast pulse seen with the spy
channel
tpulse lt tsampling. Digitization made possible by
the Nyquist filter ffilter 1/4 fsampling
Latency 300ns.
t0300ns
Input pulse
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Time budget

• ADC pipeline latency 912.5ns 112.5 ns.
• FPGA input 25 ns.
• Nyquist filter 100 ns.
• Tunnel -gt CH propagation 100 ns.
• Left-right time diff 100 ns.
• TAC response 300 ns.
• TOTAL 0.74 ms.
• Note TAC output very likely can be made faster.

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Software and firmware development tools

• Entry-level software development.
• All development tools are free.
• FPGA XILINX WebPack ISE.
• Embedded micro Keil C compiler, code restricted
  to 4kB.
• PC GUI Shareware edition of BlackBox Component
  Builder.
• Expert-level software development.
• All tools discounted for universities.
• FPGA.
• VHDL tools XILINX ISE, full version.
• Graphical tools MatLab and XILINX System
  Generator.
• Embedded micro Keil C compiler, full version.
• PC GUI Full edition of BlackBox Component
  Builder.

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Obstacles and showstoppers

• Obstacles.
• Firmware software development takes time.
• Need an expert at the Phobos end.
• Only one board exists, two more being assembled,
  all are already booked.
• The 1st board has not been fully tested yet.
• Showstoppers?
• Does Phobos need this tool?
• Can Phobos designate an expert?
• Recent deep cut in funding cannot be ignored.

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Summary

• The technology is under control.
• Glitches, if any, will be resolved.
• One DDC-8 assembled, works OK, but not yet fully
  tested.
• Two more boards being assembled.
• Firmware software development will take time.
• A possible showstopper recent cut in funding.
• Does Phobos need this device?
• My personal belief if there is need, the expert
  will step forward.
• The situation looks good, but not hopeless.