Introduction to Multiprocessor System-on-Chip

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Introduction to Multiprocessor System-on-Chip

• Prof. Jan Madsen
• Informatics and Mathematical Modeling
• Technical University of Denmark
• Richard Petersens Plads, Building 321
• DK2800 Lyngby, Denmark

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Embedded systems
io
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Embedded systems

• Systems which use a computer to perform a
  specific function, but are neither used nor
  perceived as a computer
• They are embedded within larger electronic
  devices
• Repeatedly carrying out a particular function
• Often completely unrecognized by the devices user

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Embedded systems design
Separated validations
Prototype realization
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Principples of Codesign
void UnitControl() up down 0 open
1 while (1) while (req floor)
open 0 if (req gt floor) up 1
else down 1 while (req ! floor)
open 1 delay(10)
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Overview

• Technology
• Processors
• IC fabric
• Codesign for speed-up
• component execution timing (SW and HW)
• Building sub-system
• Hardware/software partitioning
• Building system
• System-level issues of codesign

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Software

• Elements of computation
• Store data
• Transform data
• Move data

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Processor
func
if ...
then ...
else ...
for ... ..

• Architecture components
• Processing elements transform data
• Memories store data
• Interconnect move data

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Processor General Purpose
func
if ...
then ...
else ...
for ... ..

• Availability
• Low cost (mass production)
• Simple design flow
• High flexibility

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Processor General Purpose - example
p1
func
if ...
inst mem
controller
datapath
data mem
then ...
else ...
ir
cu
func
for ... ..
reg

pc
/-
x x Ai p1
5 cycles
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Processor Custom (ASIC)
func
if ...
then ...
else ...
for ... ..

• High performance
• Low power
• Complex design flow
• No flexibility

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Processor Custom (ASIC) example
p1
func
if ...
controller
datapath
then ...
else ...
cu
mem
Ai
for ... ..


/-
x x Ai p1
1 cycle
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Processor Semicustom (ASIP)
func
if ...
then ...
else ...
for ... ..

• Costumized datapath 16, 8 or 4 bit
• Optimized for particular class of programs - MACC
• Simple design flow
• High flexibility

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Processor Semicustom - example
p1
func
if ...
inst mem
controller
datapath
data mem
then ...
else ...
ir
cu
func
Ai
for ... ..
reg


pc
/-
x x Ai p1
2 cycles
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IC fabrics

• IC is an interconnection of transistors following
  one of several possible styles fabrics
• The fabric defines how and when transistors are
  composed
• the material of processors
• IC fabrics differ in terms of customizability and
  generality

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IC fabrics Custom

• Exact implementation of processor components
• High NRE cost mask set 1M

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IC fabrics Semicustom

• Several semicustom fabrics
• Library of standard cells
• Cell arrays (sea-of-gates)
• Most processing steps are pre manufactured (high
  volume)

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IC fabrics Programmable

• Set of interconnected modules
• Set of modules programmed to implement different
  components
• FPGA
• Programmable logic modules, storage and
  interconnect

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Chips Implementing IC fabric
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Hardware/software codesign?

• Many possible mappings
• Processor may not exist yet!
• Exploring the design space
• Need to estimate

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Hardware/Software Codesign

• Optimizing
• Timing (high performance, hard deadlines)
• Area (cost)
• Power consumption
• Flexibility
• Reliability
• ...
• We will focus on timing

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Processing element timing

• Execution path
• Control data dependent
• Input data dependent
• Function implementation
• Component architecture
• Compiler or synthesis

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Formal execution path timing analysis
b1
if ...
b3
b2
else ...
then ...
for ... ..
b4
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Formal execution path timing analysis
b2
then ...
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Memory models

• Access time
• Control overhead
• Burst access (packets)
• Cache
• hit/miss time overhead
• Based on execution history

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Advanced architectures

• Modern high performance processors includes
  architectural features which complicates timing
  analysis
• Dynamic instruction scheduling
• Speculative execution
• Though fast, it makes
• the processor very power hungry
• tight bounds on timing very difficult
• Computation less predictable
• Issues which are important for embedded systems

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Building sub-systems
func
if ...
then ...
else ...
for ... ..

• Initial codesign problem
• Hardware/software partitioning
• the LYCOS cosynthesis tool
• Automatic partitioning from C (subset) and VHDL
  (single process)
• Developed at DTU

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Hardware/Software partitioning
func
b1
if ...
b2
b3
then ...
else ...
b4
for ... ..
CPU
ASIC
CPU
ASIC
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Architectural choices

• Which processor should be selected and how fast
  should it be?
• Which ASIC technology should be chosen and how
  fast should the ASIC be?
• How large an ASIC can we afford and which
  functions should it execute?
• How should the processor and ASIC communicate?

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Partitioning Model

• Determines granularity and simplifying
  assumptions w.r.t. communication, HW sharing, etc

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Estimation
SW
HW
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Process communication
b1
if ...
b2
b4
else send(...) receive(...)...
then ...
for ... ..
b3
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Solving the Partitioning Problem
SW
HW
1
2
3
4
5
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Just try all combinations...
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Solving the Partitioning Problem
Parallel execution non-additive areas
Interleaved communication additive areas
No communication interleaved exec. additive areas
Knapsack Stuffing
Large scale linear/nonlinear integer programming
Heuristics needed!
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LYCOS Design Flow
Specification
Require
Functional
Translate
SW
Analysis
CDFG
SW Estim.
Model
HW
Partitioning
HW Estim.
Model
Comm.
Comm. Estim.
Model
CDFG
HW
SW
Comm.
Synthesis
Synthesis
Synthesis
Assembler
Netlist
SW/HW
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Building Systems

• Platform architectures are heterogeneous
• Different processing element types
• Different interconnection networks and
  communication protocols
• Different memory types
• Different scheduling and synchronization
  strategies

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Managing HW platform complexity

• Development of APIs to hide complexity from
  application programmer and improve portability
• Specialized RTOS to control resource sharing and
  interfaces
• aComplex multi-level HW/SW architecture

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Software architecture
pe1
mem

private
application
RTOS
RTOS-APIs
shared
private
private
drivers
private
Cache
Bus
ce1
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Platform design challenges

• Integration
• Design process integration
• Heterogeneous component and language integration
• Design space exploration and optimization
• Verification

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Complex run-time interdependencies
PE
PE
CoP

• Run-time dependencies of independent components
  via communication
• Influence on timing and power
• Need to handle resource sharing
• Process/task scheduling
• Communication scheduling
• Scheduling strategies (static, dynamic, time or
  priority driven)

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Interdependency example

• Complex non-functional interdependencies
• Periodic task executing on PE
• Task writes to bus at the end of each periodic
  execution

Short execution time ahigh bus load
long execution time alow bus load
Local decision on improving performance may
impact the global system performance
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System-on-Chip challenge
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Network-on-Chip

• Multi-hop
• Segmented communication
• Concurrency
• Multiple simultaneous communications

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Network-on-Chip

• Multi-hop
• Segmented communication
• Concurrency
• Multiple simultaneous communications
• Sharing
• Quasi-simultaneous resource usage
• Multiple communication events occupying some or
  all resources in an interleaved fashion

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System-on-Chip design
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New design paradigme ...
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thank you!