Optimal Global Interconnecting Devices for GSI

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Optimal Global Interconnecting Devices for GSI

• Azad Naeemi, Jeffrey A. Davis
• and James D. Meindl
• Georgia Institute of Technology
• Microelectronics Research Center
• 12/10/2002

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Outline

• Motivation
• Optimal Global Wire Width
• Impact of Non-Ideal Return Paths
• Delay Variation and Repeater Area
• Crosstalk
• Conclusions

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Outline

• Motivation
• Optimal Global Wire Width
• Impact of Non-Ideal Return Paths
• Delay Variation and Repeater Area
• Crosstalk
• Conclusions

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Historic Trend
Optimal Repeaters
Dchip
Tcycle
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Historic Trend
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Interconnect Era

• Interconnect latency has become important it
  will become dominant in future.
• Wiring resource has become limited compared to
  transistor resource it will become extremely
  limited in future.
• Global interconnects should be used optimally.

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Outline

• Motivation
• Optimal Global Wire Width
• Impact of Non-Ideal Return Paths
• Delay Variation and Repeater Area
• Crosstalk
• Conclusions

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Main Question
What are the optimal wire dimensions for global
interconnects?
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Key ParametersLatency and Bisectional Bandwidth
Small latency leads to faster communication. Large
bisectional bandwidth to transfer larger number
of bits per unit time.
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Impact of Wire Width on Latency
A 24 mm long wire in the 45 nm technology node
Latency, ? (ps)
Wire Width, W (?m)
Its been assumed that optimal repeaters are
used, all dimensions are scaled proportionally.
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Data Flux Density
x
Dchip
Maximizing data flux density maximizes
bisectional bandwidth.
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Impact of Wire Width on ?D
A 24 mm long wire in the 45 nm technology node
Latency, ? (ps)
Data Flux Density, ?D (Ghz/?m)
Wire Width, W (?m)
In the RC regime, data flux density is constant,
and it drops in the RLC regime.
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Optimal Wire Width
A 24 mm long wire in the 45 nm technology node
Latency, ? (ps)
?D / ? (Ghz/?m)
Wire Width, W (?m)
In the shallow RLC region ?D /? is maximized (?
1.33ToF)
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An Example
Design of the interface between a cache memory
and a logic core
(2n)-Bit (n)-Bit
(n/2)-Bit WWopt/2
WWopt W2Wopt
Latency 1.70 Latency 1
Latency 0.86 Total B.w.1.17 Total
B.w.1 Total B.w.0.58
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Derivation of Optimal width
Delay of an RLC interconnect with optimal
repeaters 1
Optimal wire width can be found by solving
Assuming that there is an ideal return path
1 R. Venkatesan et al., ASIC SoC Conf., Sept.
2002.
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Optimal Wire Width
Rigorous value for the optimal wire width
Wopt is determined by ?
resistivity of metal, R0C0 intrinsic
delay of repeaters ? geometry of
wires ?.
Wopt is independent of interconnect length it
can be used for virtually all global
interconnects.
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Outline

• Motivation
• Optimal Global Wire Width
• Impact of Non-Ideal Return Paths
• Delay Variation and Repeater Area
• Crosstalk
• Conclusions

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Return Path
Off-chip interconnects with a nearby ground plane
On-chip interconnects over orthogonal lines
What is the optimal wire width when there is no
nearby ground plane?
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Single Line Case
RC Region RLC Region
Wopt 0.58 ?m
?D / ? (Ghz/?m)
Latency, ? (ps)
Wire Width, W (?m)
2
Optimal wire width is smaller than that of the
ideal case.
2 A. Naeemi et al., IEDM Technical Digest,
Dec. 2001.
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Two Line Case
Since both in-phase and out-of-phase switching
may happen, geometry mean of the two optimal
widths is used to maximize the average BW/?.
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Outline

• Motivation
• Optimal Global Wire Width
• Impact of Non-Ideal Return Paths
• Delay Variation and Repeater Area
• Crosstalk
• Conclusions

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Delay Variation
For W Wopt
Normalized Delay Variation (?dif - ?com)/ ?com
Wire Width, W (?m)
Using Wopt makes the dynamic delay variation due
to different switching patterns less than 3 in a
typical case.
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Total Repeater Area
Chip Area 576mm2
Arep 0.01Achip
Total Repeater Area, Arep (mm2)
Wire Width, W (?m)
Smaller total interconnect length Fewer
repeaters in the RLC regime
W??
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Outline

• Motivation
• Optimal Global Wire Width
• Impact of Non-Ideal Return Paths
• Delay Variation and Repeater Area
• Crosstalk
• Conclusions

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Crosstalk

• Optimal wire width is in the shallow RLC region.
• Both near and far aggressors contribute to noise.
• To study the impact of wire width optimization

• Ignore far lines and use the existing models for
  the near line crosstalk.
• Derive compact models for the far inductive noise

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Near Line CrosstalkImpact of Optimal Wire Width
The 45 nm technology node
Using Wopt makes crosstalk small and constant
(less than 0.15Vdd) in all generations of
technology.
2 A. Naeemi et al., IEDM Technical Digest,
Dec. 2001.
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Far Inductive NoiseCase 1 Identical Victim
Aggressor Lines
Scalar c
Scalar c
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HSPICE Verification
Rtr40? Length10mm WHST2?m ?r 3.9
?
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Far Inductive NoiseCase 2 Non-Identical Victim
Aggressor Lines
Loosely coupled assumption
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HSPICE Verification
Rtr40? Length10mm WHST2?m ?r 3.9
?
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Far Inductive CrosstalkImpact of optimal wire
width
?
The 45 nm technology node
Using Wopt makes near and far crosstalk small and
constant (less than 0.2 Vdd) in all generations
of technology.
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Outline

• Motivation
• Optimal Global Wire Width
• Impact of Non-Ideal Return Paths
• Delay Variation and Repeater Area
• Crosstalk
• Conclusions

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Conclusions

• A new interconnect-centric methodology
• Optimal wire width which maximizes Bw/?.
• Affordable global repeater area
• Small delay variation due to different switching
  patterns.
• New compact physical models for far inductive
  noise.
• Small and constant crosstalk for all generations
  of technology.