GANDALF Framework Status Report

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GANDALF FrameworkStatus Report

• GPD Meeting
• Florian Herrmann
• 25.03.2009

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High Performance RPD Readout

• Simulations for time and amplitude extraction
  from PMT signals
• Double Pulse Simulations
• Performance measurements
• First GANDALF Boards produced, commissioned
• First readout of 4 RPD channels
• Software design in progress

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Fit Algorithms for time extraction

• Spline interpolation

Use first or second derivative to define pulse
time

• 12bit _at_ 1 GspsDigitízation
• Cubic Splines
• Solve set oflin. equations
• We also tried3 dim fit in first derivation

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Fit Algorithms for time extraction

• Analog Constant Fraction

• Need no higher order Fits
• Find best Delay and Fraction values A/B?
• Linear Fit find zero point
• No Timewalk

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Find best Fraction Factor
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Timing Resolution
Methods converge at low amplitudes
Analog Constant Fraction reaches good timing
resolution with very low calculation efforts!
Spline algorithm reaches better timing resolution
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Double Pulses

• Best achievable resolution fornear following
  pulses
• Digital signal process developedfor double
  risetime range

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Performance Measurements

• How do we qualify our readout results?Noise,
  produced by analog cirucits, digitization, device
  power supply Nonlinearity, produced by signal
  amplifier, analog digital converter, board
  routing/designClock Quality, affected by
  Jitter, Time Intervall Error, Clock source
  stabilityThermal and long time stablility,
  special cooling heatsink in production

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How measure Nonlinearity?
Fourier Transform
Noise
NONL
Signal to Noise

• 60dB SNR at 4V signals corresponds to 4mV noise

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Low Effects by Nonlinearity
Noise
NONL
Difference
Pulse Simulations Measured Nonlinearities show
less effects in timing resolution lt 5
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Sampling Clock Quality

• Jitter of sampling clock reduces Effective
  Number of Bits
• Increases noise on signal
• High Precision Clock Source needed!

ENOB SNR -1,76 / 6,02
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SNR Measurement Results
Analog Circuit Normal Mode
Measured with GANDALF
LMH6552
ADS5463
ADC
fin
All 16 Channels of two AMC show good results!
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2. Harmonic Distortion
Fundamental Frequency fin (1. Harmonic)
Measured with GANDALF
Second Harmonic 2fin
Analog Circuit Normal Mode
LMH6552
ADS5463
ADC
fin
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Sampling Clock Jitter
LMH6552
AnalogIN
ADC
505,44MHz
155,52MHz
HF Synth
TCS
LMH6552
AnalogIN
ADC
500MHz
20MHz
HF Synth
OXCO
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GANDALF as Transientrecorder
8 Channel AD Conversion _at_ 500Msps 12bit or _at_
400Msps 14bit, 16bit offset DAC
Compact Flash Memory
VME64x Interface to VME CPU
VME Interface, Board Config.
To Backplane
8 Analog Inputs
16 Trigger Channels via VXS to Trigger Switch
Data Processing, Analog Trigger Generation
HF CLK
USB
To Backplane
Trigger Clock
TCS
8 Channel AD Conversion _at_ 500Msps 12bit or _at_
400Msps 14bit, 16bit offset DAC
Memory Controller
To Transition
8 Analog Inputs
S-Link Interface via P2
QDRII 144Mb
DDR2 4Gb
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AMC normal mode
8 Analog Inputs
Data Bus to GANDALF Board
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AMC interleaved mode
ADC
Analog Circuit
ADC
Analog Circuit
ADC
Analog Circuit
ADC
HF Synthe- sizer
HF Fanout
Analog Circuit
4 Analog Inputs interleaved
Data Bus to GANDALF Board
ADC
Analog Circuit
ADC
Analog Circuit
ADC
Analog Circuit
ADC
AMC EEPROM
Analog Circuit
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Time Interleaved Mode
38.88MHz Exp. Clock
DSPLL Clock System
ADC
FPGA
AI
500MHz 0
Analog IN
500MHz 180
500MHz 0
ADC
AI

• Advantage High Resolution _at_ High Rate ? 12bit
  _at_1Gsps
• Challenges
• Symmetric clock distribution
• Clock Jitter lt 1ps
• Symmetric placement of devices
• Possible errors
• Gain error
• Clock skew
• Offset/Slack

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Input Range and DACs
0V
4V Range
-4V
Set 4V range to any value between this
configurations (0.3mV Step)
2V
4V Range
-2V
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10bit ENOB interleaved
1GHz sampling rate Offset correction by DAC Gain
correction by FPGA
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First Gandalf RPD Data
NIM Coincidence
A9up
A9dn
GANDALF
B18up
B18dn
0
1
Port
2
HVs
3
USB Readout
Ext Trg
TDS6000 Oscilloscope
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First GANDALF RPD Data

• Very good noise performance lt0.9 mV
• Calculate Time and Amplitudes offline
• To be compared with our simulated Pulses

Interleaved Channels
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GANDALF Framework
RPD Trigger Switch Physics PCB Software
Transientrecorder AMC (SS) Time Simulation
(SB) NL Simulation (GK)
FPGA TDC Software (AW) PCB
Veto Matrix Software (Mainz) PCB (s.o.)
GANDALF PCB (FH) CPLD VME Software (LL) FPGA
Software (FH)
GANDALF TEST Setup PCB Mechanics (FH) Software
(XJ)
Arwen Aragon THGEM Readout Software PCB
GANDALF Portable Slink Ethernet Adapter
Mechanics (s.o.) Software (s.o.)
GANDALF on the lattice PCB Software
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Backup
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Buffered Pulses Readout
BOS
Exp Clk
1 GHz Clk
Trigger
1
2
3
Latency
Latency
Latency
Window
Window
Window
Frame2
Frame1
Frame3
Input
TS1
TS2
TS3
0
t
Frame Buffer
aCFD
aCFD
TS1
TS2
TS3
Data Buffer
TA 1
TA 3
Rel time
Rel time
Abs time
Slow Counter
Fast Counter
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Pipelined Pulses Readout
BOS
Exp Clk
1 GHz Clk
Trigger
1
2
3
Latency
Latency
Latency
Window
Window
Window
Frame2
Frame1
Frame3
Input
TS1
TS2
TS3
TA
TA
TA
0
t
Data Buffer
TA 1
TA 3
TA 1
Rel time
Rel time
Rel time
Abs time
Slow Counter
Fast Counter
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AMC Data Readout ilm
Port_n_n1 ILM Analog IN
amc_conf .gain
Gain
5us Ringbuffer 10 FIFO_Modules
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event frames, 128 Gsps samples
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Gain
Adress Counter, Trg Loop
Trigger ( 1 1 25)
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Trigger System for RPD
Analog Inputs
GANDALF
VXS Backplane
Protonen
COMPASS Trigger
Exp. Clock
Pionen
COMPASS DAQ
Proton Trigger
GANDALF
Trigger Switch
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Jitter Definitons
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