CSE245: Computer-Aided Circuit Simulation and Verification - PowerPoint PPT Presentation

About This Presentation
Title:

CSE245: Computer-Aided Circuit Simulation and Verification

Description:

Extraction. Parasitics resistance, capacitance. and inductance cause noise , ... Parasitic Extraction. R,L,C Extraction. Model Order Reduction. Moment Matching ... – PowerPoint PPT presentation

Number of Views:75
Avg rating:3.0/5.0
Slides: 22
Provided by: vincen61
Learn more at: https://cseweb.ucsd.edu
Category:

less

Transcript and Presenter's Notes

Title: CSE245: Computer-Aided Circuit Simulation and Verification


1
CSE245 Computer-Aided Circuit Simulation and
Verification
  • Lecture Note 4
  • Model Order Reduction (2)
  • Spring 2008
  • Prof. Chung-Kuan Cheng

2
Model Order Reduction Overview
  • Explicit Moment Matching
  • AWE, Pade Approximation
  • Implicit Moment Matching (Projection Framework)
  • Krylov Subspace Methods
  • PRIMA, SPRIM
  • Gaussian Elimination
  • TICER, Y-Delta Transformation

3
Conventional Design Flow
Parasitics resistance, capacitance and
inductance cause noise , energy consumption and
power distribution problem
Function Sepc
Beh. Simul
RTL
Logic Synth.
Stat. Wire Model
Gate-Lev. Sim
Gate-level Net.
Front-end
Back-end
Floorplanning
Para. Extraction
Place Route
Layout
4
Parasitic Extraction
R,L,C Extraction
Model Order Reduction
5
Moment Matching Projection method
  • Key ideal of Model Order reduction
  • Moments Matching and Projection
  • Step1 identify internal state function and
    variables.
  • Step2 Compose moments matching. (Pade, Taylor
    expression).
  • Step3 Project matrix with matching moments.
    (Block Arnoldi (PRIMA) or block Lanczos (PVL))
  • Step4 Get the reduced state function.

6
Explicit V.S. Implicit Moment Matching
  • Explicit moment matching methods
  • Numerically ill-conditioned
  • Implicit moment matching methods
  • construct reduced order models through
    projection, or congruence transformation.
  • Krylov subspaces vectors instead of moments are
    used.

7
Congruence Transformation
  • Definition
  • Property Congruence transformation preserves
    semidefiniteness of the matrix

8
Krylov Subspace
  • Given an n x q matrix Vq whose column vectors are
    v1, v2, , vq. The span of Vq is defined as
  • Given an n x n matrix A and a n x 1 vector r the
    Krylov subspace is defined as

9
PRIMA
  • Passive Reduced-order Interconnect Macromodeling
    Algorithm.
  • Krylov subspace based projection method
  • Reduced model generated by PRIMA is passive and
    stable.

PRIMA
(system of size q, qltltn)
(system of size n)
where
10
PRIMA
  • step 1. Circuit Formulation
  • step 2. Find the projection matrix Vq
  • Arnoldi Process to generate Vq

11
PRIMA Arnoldi
12
PRIMA
  • step 3. Congruence Transformation

13
PRIMA Properties
  • Preserves passivity, and hence stability
  • Matches moments up to order q (proof in next
    slide)
  • Original matrices A and C are structured.
  • But and do not preserve this structure in
    general

14
PRIMA Moment Matching Proof
Used lemma 1
15
PRIMA Lemma Proof
16
SPRIM
  • Structure-Preserving Reduced-Order Interconnect
    Macromodeling
  • Similar to PRIMA except that the projection
    matrix Vq is different
  • Preserves twice as many moments as PRIMA
  • Preserves structure
  • Preserves passivity, stability and reciprocity
  • Matching the same number of moment as PRIMA, but
    preserve the structure which can reduced
    numerical calculation.

17
SPRIM
  • Recall
  • Suppose Vq is generated by Arnoldi process as in
    PRIMA. Partition Vq accordingly
  • Construct New Projection Matrix

18
SPRIM
  • Congruence Transformation
  • Now structure is preserved
  • Transfer function for the reduced order model

19
Traditional Y-? Transformation
  • Conductance in series
  • Conductance in star-structure

n0
n1
n2
n1
n2
n1
n1
n0
n3
n2
n2
n3
20
TICER (TIme Constant Equilibration Reduction)
  • 1) Calculate time constant for each node
  • 2) Eliminate quick nodes and slow nodes
  • Quick node Eliminate if
  • Slow node Eliminate if
  • 3) Insert new Rs/Cs between former neighbors of
    N
  • If nodes j and k had been connected to N through
    gjN and gkN, add a conductance of value
    gjNgkN/GN between j and k
  • If nodes j and k had been connected to N through
    cjN and gkN, add a capacitor of value cjNgkN/GN
    between j and k

21
TICER Issues
  • Fill-in
  • The order that nodes are eliminated matters
  • Minimum Degree Ordering can be implemented to
    reduce fill-in
  • May need to limit number of incident resistors to
    control fill-in
  • Error control leads to low reduction ratio
  • Accuracy
  • Matches 0th moment at every node in the reduced
    circuit.
  • Only Correct DC op point guaranteed
Write a Comment
User Comments (0)
About PowerShow.com