News from Annecy Virgo electronic developments

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News from Annecy Virgo electronic developments
Cascina
24/01/2007
Nicolas LETENDRE
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TOLM Board
User SignalsGeneration
Local Clockcontrol
UserSignalsOutput
IRIG BDecoding
LocalClock
1PPS
IRIG B
GPS Time
ConfigurationRegisters
From/ToPC
Data Packet Emitter
BUS PCI
2 opticalOutputs
64-bit _at_66MHz
1.6 Gbit/s
From/ToDSP boars
Link ports
2 OpticalInputs
Data Packet Receiver
100 Mo/s
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View of TOLM V1
Optical Transceiver_at_ 1.6 Gbit/s in SFP format
Link ports
FPGA
IRIG-Binput
User Signalsoutputs
Local Clock
PCI bus
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TOLM Status

• No major hardware problems found
• Routinely used for tests (Timing, ADC)
• Basic function available but still a lot of VHDL
  writing to build the firmware
• A new version has to be designed in order to
  support 64-bit PCI bus _at_ 66 MHz
• 8 new TOLM V1 has been received for tests purpose

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New Virgo Timing system
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Timing Distribution Box - TDBox

• Fully tested and Ready for production

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Timing Tests
TOLM
TOLM
TDBox
TDBox
IRIG-B
Diff.RJ45
optic
Optic Up to 3Km
GPSReceiver
TTL
PC

• Monitoring of timing parameters
• GPS time
• Timing flags
• Control loop feedback error
• Tests during few weeks
• No major problems, except small timing jumps
  under investigation

Storage
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ADC Board features

• Analog part
• ADC AD7474 18-bit _at_ 800kHz
• 16 ADC channels
• Mezzanine anti-alias and compression filter
• Differential or single-ended input
• Digital Part
• 8th order digital filters New DSP
  investigation for cost and performances reasons
• Decimation to reduce the output data rate
• On board Timing system to stamp data with the GPS
  time
• Communication through optic fiber for data
  transmission and board configuration

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ADC Board overview
SER/DES
SFP transceiver
VME
FPGA
RJ45
IRIG-B
Analog Input
FPGA
DSP
VME
Power supplies
Clock output
LEMO
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ADC Board status

• Tests have to be performed for the DSP selection
• We have to check the data transfers.
• CAO will start soon
• First prototype expected beginning of June 2007

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DSP selection
DATA
FPGA eval boardData source
DSP Sharc eval board
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Mux/Demux Board
Optic fibers
decoding
Optical Emit./Rec
1
2
3
Header of packet
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FPGA

• Route data packets from n inputs to 1 output
• Route data packets from 1 input to n outputs
• Work in standalone (dont need to configure)

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6
7
8
Mux/DeMux board
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MUX-DEMUX Board
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MUX-DEMUX status

• First prototypes tested
• No hardware problems found
• Some VHDL code has to be written

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Conclusion

• TOLM
• 12 TOLM V1 are working for test purpose
• TOLM V2 has to be designed
• ADC Board
• ADC board first prototype for June 2007
• Timing System - TDBox
• First prototype of TDBox is OK
• Production should start soon
• Mux-Demux
• The first prototype is OK

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Questions ???