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Week 12/ Lecture 22 Nov. 17, 2005

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Prof. Fearing. 6. Clocked S-R Flip-Flop. When CK = 0, the value of Q ... Prof. Fearing. 7. The output terminals Q and Q behave just as in the S-R flip-flop. ... – PowerPoint PPT presentation

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Title: Week 12/ Lecture 22 Nov. 17, 2005


1
Week 12/ Lecture 22 Nov. 17, 2005
  • Overview of Digital Systems
  • CMOS Inverter
  • CMOS Gates
  • Digital Logic
  • Combinational Blocks
  • Latches and Flip Flops
  • Registers and Counters
  • Reading Hambley 12.7, 7

2
Decoder
  • n inputs, 2n outputs
  • one output is 1 for each possible input pattern,
    all other outputs are 0

1 2 3 4
A B
3
Multiplexer (MUX)
  • n-bit selector and 2n inputs, one output
  • output equals one of the inputs, depending on
    selector

I1 I2 I3 I4
O
2 input decoder
A B
4
Flip-Flops
  • One of the basic building blocks for sequential
    circuits is the flip-flop
  • 2 stable operating states ? stores 1 bit of info.
  • A simple flip-flop can be constructed using two
    inverters

Q
Q
5
Realization of the S-R Flip-Flop
S
Q
Q
R
S-R Flip-Flop Symbol
R S Qn
0 0 Qn-1
0 1 1
1 0 0
1 1 (not allowed)
6
Clocked S-R Flip-Flop
  • When CK 0, the value of Q does not change
  • When CK 1, the circuit acts like an ordinary
    S-R flip-flop

7
The D (Delay) Flip-Flop
D
Q
D Flip-Flop Symbol
CK
Q
  • The output terminals Q and Q behave just as in
    the S-R flip-flop.
  • Q changes only when the clock signal CK makes a
    positive transition.

CK D Qn
0 ? Qn-1
1 ? Qn-1
? 0 0
? 1 1
8
D Flip-Flop Example (Timing Diagram)
CK
t
D
t
Q
t
9
Registers
  • A register is an array of flip-flops that is used
    to store or manipulate the bits of a digital
    word.
  • Example 4 bit data register

OUT1
OUT2
OUT3
OUT4
"0"
R
S
R
S
R
S
R
S
D
Q
D
Q
D
Q
D
Q
CLK
IN1
IN2
IN3
IN4
10
Registers
  • Example Serial-In, Parallel-Out Shift Register

Q0
Q1
Q2
Parallel outputs
D0
Q0
D1
Q1
D2
Q2
Data input
CK
CK
CK
Clock input
Parallel to serial converter
11
Shift Register Application
  • Parallel-to-serial conversion for serial
    transmission

parallel outputs
parallel inputs
serial transmission
12
Finite State Machine Block diagram/Counter example
outputs
Register (NM edge triggered flip-flops)
Inputs (N)
next state
present state
Combinatorial Logic
Qn1
Q2 Q1 Q0 Q2 Q1 Q0








Clock
Current state of the system Qn (M states)
Clock
NSPS1
(good for freq division, position, velocity
sensing)
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