CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH

1
CS151BComputer Systems ArchitectureWinter 2002
TuTh 2-4pm - 2444 BH
Lecture 6 ALU Design II Multiply, Divide,
and Floating Point Operations

• Instructor Prof. Jason Cong
• ltcong_at_cs.ucla.edugt

2
Review ALU Design

• Bit-slice plus extra on the two ends
• Overflow means number too large for the
  representation
• Carry-look ahead and other adder tricks

32
A
signed-arith and cin xor co
a0
b0
a31
b31
4
ALU0
ALU31
M
cin
co
cin
co
s0
s31
C/L to produce select, comp, c-in
32
Ovflw
S
3
Review Elements of the Design Process

• Divide and Conquer (e.g., ALU)
• Formulate a solution in terms of simpler
  components.
• Design each of the components (subproblems)
• Generate and Test (e.g., ALU)
• Given a collection of building blocks, look for
  ways of putting them together that meets
  requirement
• Successive Refinement (e.g., multiplier, divider)
• Solve "most" of the problem (i.e., ignore some
  constraints or special cases), examine and
  correct shortcomings.
• Formulate High-Level Alternatives (e.g., shifter)
• Articulate many strategies to "keep in mind"
  while pursuing any one approach.
• Work on the Things you Know How to Do
• The unknown will become obvious as you make
  progress.

4
Review Summary of the Design Process
Hierarchical Design to manage complexity Top
Down vs. Bottom Up vs. Successive
Refinement Importance of Design
Representations Block Diagrams
Decomposition into Bit Slices Truth Tables,
K-Maps Circuit Diagrams Other
Descriptions state diagrams, timing diagrams,
reg xfer, . . . Optimization Criteria
Gate Count Package Count
top down
bottom up
Logic Levels Fan-in/Fan-out
Area
Power
Delay
Cost
Design time
Pin Out
5
MIPS arithmetic instructions

• Instruction Example Meaning Comments
• add add 1,2,3 1 2 3 3 operands
  exception possible
• subtract sub 1,2,3 1 2 3 3 operands
  exception possible
• add immediate addi 1,2,100 1 2 100
  constant exception possible
• add unsigned addu 1,2,3 1 2 3 3
  operands no exceptions
• subtract unsigned subu 1,2,3 1 2 3 3
  operands no exceptions
• add imm. unsign. addiu 1,2,100 1 2 100
  constant no exceptions
• multiply mult 2,3 Hi, Lo 2 x 3 64-bit
  signed product
• multiply unsigned multu2,3 Hi, Lo 2 x 3
  64-bit unsigned product
• divide div 2,3 Lo 2 3, Lo quotient, Hi
  remainder
• Hi 2 mod 3
• divide unsigned divu 2,3 Lo 2
  3, Unsigned quotient remainder
• Hi 2 mod 3
• Move from Hi mfhi 1 1 Hi Used to get copy of
  Hi
• Move from Lo mflo 1 1 Lo Used to get copy of
  Lo

6
MULTIPLY (unsigned)

• Paper and pencil example (unsigned)
• Multiplicand 1000
  Multiplier 1001 1000
  0000 0000 1000 Product
  01001000
• m bits x n bits mn bit product
• Binary makes it easy
• 0 gt place 0 ( 0 x multiplicand)
• 1 gt place a copy ( 1 x multiplicand)
• 4 versions of multiply hardware algorithm
• successive refinement

7
Unsigned Combinational Multiplier

• Stage i accumulates A 2 i if Bi 1
• Q How much hardware for 32 bit multiplier?
  Critical path?

8
How does it work?
0
0
0
0
0
0
0
B0
B1
B2
B3
P0
P1
P2
P3
P4
P5
P6
P7

• at each stage shift A left ( x 2)
• use next bit of B to determine whether to add in
  shifted multiplicand
• accumulate 2n bit partial product at each stage

9
Unisigned shift-add multiplier (version 1)

• 64-bit Multiplicand reg, 64-bit ALU, 64-bit
  Product reg, 32-bit multiplier reg

Shift Left
Multiplicand
64 bits
Multiplier
Shift Right
64-bit ALU
32 bits
Write
Product
Control
64 bits
Multiplier datapath control
10
Multiply Algorithm Version 1
Start
Multiplier0 1
Multiplier0 0
1a. Add multiplicand to product place
the result in Product register

• Product Multiplier Multiplicand 0000 0000
  0011 0000 0010
• 0000 0010 0001 0000 0100
• 0000 0110 0000 0000 1000
• 0000 0110

2. Shift the Multiplicand register left 1 bit.
3. Shift the Multiplier register right 1 bit.
32nd repetition?
No lt 32 repetitions
Yes 32 repetitions
Done
11
Observations on Multiply Version 1

• 1 clock per cycle gt ? 100 clocks per multiply
• Ratio of multiply to add 51 to 1001
• 1/2 bits in multiplicand always 0gt 64-bit adder
  is wasted
• 0s inserted in left of multiplicand as
  shiftedgt least significant bits of product
  never changed once formed
• Instead of shifting multiplicand to left, shift
  product to right?

12
MULTIPLY HARDWARE Version 2

• 32-bit Multiplicand reg, 32 -bit ALU, 64-bit
  Product reg, 32-bit Multiplier reg

Multiplicand
32 bits
Multiplier
Shift Right
32-bit ALU
32 bits
Shift Right
Product
Control
Write
64 bits
13
How to think of this?

• Remember original combinational multiplier

14
Simply warp to let product move right...
0
0
0
0
B0
B1
B2
B3
P0
P1
P2
P3
P4
P5
P6
P7

• Multiplicand stays still and product moves right

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Multiply Algorithm Version 2
Product Multiplier Multiplicand
0000 0000 0011 0010 1 0010
0000 0011 0010 2 0001 0000 0011
0010 3 0001 0000 0001 0010 1
0011 0000 0001 0010 2 0001 1000
0001 0010 3 0001 1000 0000
0010 1 0001 1000 0000 0010 2 0000
1100 0000 0010 3 0000 1100 0000
0010 1 0000 1100 0000 0010 2
0000 0110 0000 0010 3 0000 0110
0000 0010 0000 0110 0000
0010
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Still more wasted space!
Product Multiplier Multiplicand
0000 0000 0011 0010 1 0010 0000
0011 0010 2 0001 0000 0011
0010 3 0001 0000 0001 0010 1 0011
0000 0001 0010 2 0001 1000 0001
0010 3 0001 1000 0000 0010 1
0001 1000 0000 0010 2 0000 1100
0000 0010 3 0000 1100 0000
0010 1 0000 1100 0000 0010 2 0000
0110 0000 0010 3 0000 0110 0000
0010 0000 0110 0000 0010
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Observations on Multiply Version 2

• Product register wastes space that exactly
  matches size of multipliergt combine Multiplier
  register and Product register

18
MULTIPLY HARDWARE Version 3

• 32-bit Multiplicand reg, 32 -bit ALU, 64-bit
  Product reg, (0-bit Multiplier reg)

Multiplicand
32 bits
32-bit ALU
Shift Right
Product
(Multiplier)
Control
Write
64 bits
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Multiply Algorithm Version 3
Start

• Multiplicand Product0010 0000 0011

Product0 1
Product0 0
2. Shift the Product register right 1 bit.
32nd repetition?
No lt 32 repetitions
Yes 32 repetitions
Done
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Observations on Multiply Version 3

• 2 steps per bit because Multiplier Product
  combined
• MIPS registers Hi and Lo are left and right half
  of Product
• Gives us MIPS instruction MultU
• How can you make it faster?
• What about signed multiplication?
• easiest solution is to make both positive
  remember whether tocomplement product when done
  (leave out the sign bit, run for 31 steps)
• apply definition of 2s complement
• need to sign-extend partial products and subtract
  at the end
• Booths Algorithm is elegant way to multiply
  signed numbers using same hardware as before and
  save cycles
• can handle multiple bits at a time

21
Motivation for Booths Algorithm

• Example 2 x 6 0010 x 0110
  0010 x 0110 0000 shift (0 in
  multiplier) 0010 add (1 in
  multiplier) 0010 add (1 in
  multiplier) 0000 shift (0 in
  multiplier) 00001100
• ALU with add or subtract gets same result in more
  than one way 6 2 8 0110 00010
  01000 11110 01000
• For example
• 0010 x 0110 0000
  shift (0 in multiplier) 0010 sub (first 1
  in multpl.) . 0000 shift (mid
  string of 1s) . 0010 add (prior step
  had last 1) 00001100

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Booths Algorithm
middle of run
beginning of run
end of run
0 1 1 1 1 0

• Current Bit Bit to the Right Explanation Example O
  p
• 1 0 Begins run of 1s 0001111000 sub
• 1 1 Middle of run of 1s 0001111000 none
• 0 1 End of run of 1s 0001111000 add
• 0 0 Middle of run of 0s 0001111000 none
• Originally for Speed (when shift was faster than
  add)
• Replace a string of 1s in multiplier with an
  initial subtract when we first see a one and then
  later add for the bit after the last one

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Booths Example (2 x 7)
Operation Multiplicand Product next? 0. initial
value 0010 0000 0111 0 10 -gt sub

• 1a. P P - m 1110
  1110 1110 0111 0 shift P (sign ext)
• 1b. 0010 1111 0011 1 11 -gt nop, shift
• 2. 0010 1111 1001 1 11 -gt nop, shift
• 3. 0010 1111 1100 1 01 -gt add
• 4a. 0010 0010
• 0001 1100 1 shift
• 4b. 0010 0000 1110 0 done

24
Booths Example (2 x -3)
Operation Multiplicand Product next? 0. initial
value 0010 0000 1101 0 10 -gt sub

• 1a. P P - m 1110
  1110 1110 1101 0 shift P (sign ext)
• 1b. 0010 1111 0110 1 01 -gt add
  0010
• 2a. 0001 0110 1 shift P
• 2b. 0010 0000 1011 0 10 -gt sub
  1110
• 3a. 0010 1110 1011 0 shift
• 3b. 0010 1111 0101 1 11 -gt nop
• 4a 1111 0101 1 shift
• 4b. 0010 1111 1010 1 done

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MIPS logical instructions

• Instruction Example Meaning Comment
• and and 1,2,3 1 2 3 3 reg.
  operands Logical AND
• or or 1,2,3 1 2 3 3 reg. operands
  Logical OR
• xor xor 1,2,3 1 2 ??3 3 reg. operands
  Logical XOR
• nor nor 1,2,3 1 (2 3) 3 reg.
  operands Logical NOR
• and immediate andi 1,2,10 1 2
  10 Logical AND reg, constant
• or immediate ori 1,2,10 1 2 10 Logical
  OR reg, constant
• xor immediate xori 1, 2,10 1 2
  10 Logical XOR reg, constant
• shift left logical sll 1,2,10 1 2 ltlt
  10 Shift left by constant
• shift right logical srl 1,2,10 1 2 gtgt
  10 Shift right by constant
• shift right arithm. sra 1,2,10 1 2 gtgt
  10 Shift right (sign extend)
• shift left logical sllv 1,2,3 1 2 ltlt 3
  Shift left by variable
• shift right logical srlv 1,2, 3 1 2 gtgt
  3 Shift right by variable
• shift right arithm. srav 1,2, 3 1 2 gtgt 3
  Shift right arith. by variable

26
Shifters
Two kinds logical-- value shifted in is
always "0" arithmetic-- on right
shifts, sign extend
msb
lsb
"0"
"0"
msb
lsb
"0"
Note these are single bit shifts. A given
instruction might request 0 to 32 bits to be
shifted!
27
Combinational Shifter from MUXes
B
A
Basic Building Block
sel
D
8-bit right shifter

• What comes in the MSBs?
• How many levels for 32-bit shifter?

28
Barrel Shifter
Technology-dependent solutions transistor per
switch
29
Barrel Shifter (2)

• 2N-1 inputs (diagonal)
• N outputs (horizontal)
• N control signals (vertical) only one can be
  true
• Example 2-bit right logical shift
• SR21
• A0-A3 inputs
• A4 A5 1

30
Divide Paper Pencil

• 1001 Quotient
• Divisor 1000 1001010 Dividend 1000
  10 101 1010 1000 10
  Remainder (or Modulo result)
• See how big a number can be subtracted, creating
  quotient bit on each step
• Binary gt 1 divisor or 0 divisor
• Dividend Quotient x Divisor Remaindergt
  Dividend Quotient Divisor
• 3 versions of divide, successive refinement

31
DIVIDE HARDWARE Version 1

• 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder
  reg, 32-bit Quotient reg

Shift Right
Divisor
64 bits
Quotient
Shift Left
64-bit ALU
32 bits
Write
Remainder
Control
64 bits
32
Divide Algorithm Version 1

• Takes n1 steps for n-bit Quotient Rem.
• Remainder Quotient Divisor0000 0111
  0000 0010 0000

Remainder lt 0
Test Remainder
Remainder ?? 0
No lt n1 repetitions
Yes n1 repetitions (n 4 here)
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Divide Algorithm I example (7 / 2)

• Remainder Quotient Divisor 0000
  0111 00000 0010 0000
• 1 1110 0111 00000 0010 0000
• 2 0000 0111 00000 0010 0000
• 3 0000 0111 00000 0001 0000
• 1 1111 0111 00000 0001 0000
• 2 0000 0111 00000 0001 0000
• 3 0000 0111 00000 0000 1000
• 1 1111 1111 00000 0000 1000
• 2 0000 0111 00000 0000 1000
• 3 0000 0111 00000 0000 0100
• 1 0000 0011 00000 0000 0100
• 2 0000 0011 00001 0000 0100
• 3 0000 0011 00001 0000 0010
• 1 0000 0001 00001 0000 0010
• 2 0000 0001 00011 0000 0010
• 3 0000 0001 00011 0000 0010

Answer Quotient 3 Remainder 1
34
Observations on Divide Version 1

• 1/2 bits in divisor always 0gt 1/2 of 64-bit
  adder is wasted gt 1/2 of divisor is wasted
• Instead of shifting divisor to right, shift
  remainder to left?
• 1st step cannot produce a 1 in quotient bit
  (otherwise too big) gt switch order to shift
  first and then subtract, can save 1 iteration

35
Divide Algorithm I example wasted space

• Remainder Quotient Divisor 0000
  0111 00000 0010 0000
• 1 1110 0111 00000 0010 0000
• 2 0000 0111 00000 0010 0000
• 3 0000 0111 00000 0001 0000
• 1 1111 0111 00000 0001 0000
• 2 0000 0111 00000 0001 0000
• 3 0000 0111 00000 0000 1000
• 1 1111 1111 00000 0000 1000
• 2 0000 0111 00000 0000 1000
• 3 0000 0111 00000 0000 0100
• 1 0000 0011 00000 0000 0100
• 2 0000 0011 00001 0000 0100
• 3 0000 0011 00001 0000 0010
• 1 0000 0001 00001 0000 0010
• 2 0000 0001 00011 0000 0010
• 3 0000 0001 00011 0000 0010

36
Divide Paper Pencil

• 01010 Quotient
• Divisor 0001 00001010 Dividend
  00001 0001 0000
  0001 0001
  0 00 Remainder
  (or Modulo result)
• Notice that there is no way to get a 1 in
  leading digit!(this would be an overflow, since
  quotient would haven1 bits)

37
DIVIDE HARDWARE Version 2

• 32-bit Divisor reg, 32-bit ALU, 64-bit Remainder
  reg, 32-bit Quotient reg

Divisor
32 bits
Quotient
Shift Left
32-bit ALU
32 bits
Shift Left
Remainder
Control
Write
64 bits
38
Divide Algorithm Version 2

• Remainder Quotient Divisor 0000 0111
  0000 0010

Remainder ? 0
Test Remainder
Remainder lt 0
No lt n repetitions
Yes n repetitions (n 4 here)
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Observations on Divide Version 2

• Eliminate Quotient register by combining with
  Remainder as shifted left
• Start by shifting the Remainder left as before.
• Thereafter loop contains only two steps because
  the shifting of the Remainder register shifts
  both the remainder in the left half and the
  quotient in the right half
• The consequence of combining the two registers
  together and the new order of the operations in
  the loop is that the remainder will shifted left
  one time too many.
• Thus the final correction step must shift back
  only the remainder in the left half of the
  register

40
DIVIDE HARDWARE Version 3

• 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder
  reg, (0-bit Quotient reg)

Divisor
32 bits
32-bit ALU
HI
LO
Shift Left
Remainder
(Quotient)
Control
Write
64 bits
41
Divide Algorithm Version 3

• Remainder Divisor0000 0111 0010

Test Remainder
Remainder lt 0
Remainder ? 0
No lt n repetitions
Yes n repetitions (n 4 here)
42
Observations on Divide Version 3

• Same Hardware as Multiply just need ALU to add
  or subtract, and 64-bit register to shift left or
  shift right
• Hi and Lo registers in MIPS combine to act as
  64-bit register for multiply and divide
• Signed Divides Simplest is to remember signs,
  make positive, and complement quotient and
  remainder if necessary
• Note Dividend and Remainder must have same sign
• Note Quotient negated if Divisor sign Dividend
  sign disagreee.g., 7 2 3, remainder 1
• What about? 7 2 4, remainder 1
• Possible for quotient to be too large if divide
  64-bit integer by 1, quotient is 64 bits (called
  saturation)

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What is in a number?

• What can be represented in N bits?
• Unsigned 0 to 2N - 1
• 2s Complement - 2N-1 to 2N-1 - 1
• 1s Complement -2N-11 to 2N-1-1
• Excess M 2 -M to 2 N - M - 1
• (E e M)
• BCD 0 to 10N/4 - 1
• But, what about?
• very large numbers? 9,349,398,989,787,762,244,859,
  087,678
• very small number? 0.0000000000000000000000045691
  
• rationals 2/3
• irrationals
• transcendentals e, ?

44
Recall Scientific Notation
exponent
decimal point
Sign, magnitude
23
-24
6.02 x 10 1.673 x 10
radix (base)
Mantissa
Sign, magnitude
e - 127
IEEE F.P. 1.M x 2

• Issues
• Arithmetic (, -, , / )
• Representation, Normal form
• Range and Precision
• Rounding
• Exceptions (e.g., divide by zero, overflow,
  underflow)
• Errors
• Properties ( negation, inversion, if A ?? B then
  A - B ? 0 )

45
Review from Prerequisties Floating-Point
Arithmetic
Representation of floating point numbers in IEEE
754 standard single precision
1
8
23
S
E
sign
M
mantissa sign magnitude, normalized binary
significand w/ hidden integer bit 1.M
exponent excess 127 binary integer
actual exponent is e E - 127
0 lt E lt 255
S
E-127
N (-1) 2 (1.M)
0 0 00000000 0 . . . 0 -1.5 1
01111111 10 . . . 0
Magnitude of numbers that can be represented is
in the range
-126
127
-23
)
2
(1.0)
(2 - 2
to
2
which is approximately
-38
38
to
3.40 x 10
1.8 x 10
(integer comparison valid on IEEE Fl.Pt. numbers
of same sign!)
46
Basic Addition Algorithm/Multiply issues
For addition (or subtraction) this translates
into the following steps (1) compute Ye - Xe
(getting ready to align binary point) (2) right
shift Xm that many positions to form Xm 2 (3)
compute Xm 2 Ym if representation
demands normalization, then normalization step
follows (4) left shift result, decrement
result exponent (e.g., 0.001xx) right
shift result, increment result exponent (e.g.,
101.1xx) continue until MSB of data is 1
(NOTE Hidden bit in IEEE Standard) (5) for
multiply, doubly biased exponent must be
corrected Xe 7 Ye -3
Excess 8 extra subtraction
step of the bias amount (6) if result is 0
mantissa, may need to zero exponent by special
step
Xe-Ye
Xe-Ye
7 8 -3 8 4 8 8
Xe 1111 Ye 0101 10100
15 5 20
47
Extra Bits for Rounding
"Floating Point numbers are like piles of sand
every time you move one you lose a little sand,
but you pick up a little dirt." How many extra
bits? IEEE As if computed the result exactly
and rounded.
Need of extra bits For addition 1.xxxxx 1.xxx
xx 1.xxxxx 1.xxxxx 0.001xxxxx 0.01xxxxx
1x.xxxxy 1.xxxxxyyy
1x.xxxxyyy
Needed post-normalization pre-normalization
pre and post

• Guard Digits digits to the right of the first p
  digits of significand to guard against loss of
  digits can later be shifted left into first P
  places during normalization.
• IEEE 754 keeps 2 extra bits guard bit and round
  bit

48
Rouding with Guard Digits
Example 2.56x100 2.34x102 (assuming 3
significant digits)
With guard digits
Without guard digits
2.3400 2.34 0.0256
0.02 --------------------
-------------
2.3656 2.36 Rounded to 2.37

• one round digit must be carried to the right of
  the guard digit so that after a normalizing left
  shift, the result can be rounded, according to
  the value of the round digit
• ulp units in the last place
• IEEE 754 guarantees the accuracy within one-half
  ulp

49
Sticky Bit
Additional bit to the right of the round digit to
better fine tune rounding d0 . d1 d2 d3 . . .
dp-1 0 0 0 0 . 0 0 X . . . X X
X S X X S
Sticky bit set to 1 if exist any 1 bit fall
off the end of the round digit

• Allow machine to see difference between 0.5000
  vs 0.5001
• May set during addition when shifting the
  smaller number to the right

50
Rounding Methods
51
Denormalized (Subnormal) Numbers
2-bias
denorm gap
1-bias
-bias
2
2
0
2
Suppose B 2, 3-bit mantissa
The gap between 0 and the next representable
number is much larger than the gaps between
nearby representable numbers. IEEE standard uses
denormalized numbers (exp. 0 significand
ltgt0) to fill in the gap, making the distances
between numbers near 0 more alike.
2-bias
1-bias
-bias
2
2
0
2
p-1 bits of precision
p bits of precision
same spacing, half as many values!
NOTE PDP-11, VAX cannot represent subnormal
numbers. These machines underflow
to zero instead.
52
Infinity and NaNs
Not a number, but not infinity (e.q. sqrt(-4))
invalid operation exception (unless operation
is or )
S 1 . . . 1 non-zero
NaN
HW decides what goes here
NaNs propagate f(NaN) NaN
53
Pentium Bug

• Some dont-care entry was introduced incorrectly
  in a lookup-table for floating-point division
• First 11 bits to right of decimal point always
  correct bits 12 to 52 where bug can occur (4th
  to 15th decimal digits)
• FP divisors near integers 3, 9, 15, 21, 27 are
  dangerous ones
• 3.0 gt d ? 3.0 - 36 x 222 , 9.0 gt d ? 9.0 - 36 x
  220
• 15.0 gt d ? 15.0 - 36 x 220 , 21.0 gt d ? 21.0 -
  36 x 219
• 0.333333 x 9 could be problem
• In Microsoft Excel, try (4,195,835 / 3,145,727)
  3,145,727
• 4,195,835 gt not a Pentium with bug
• 4,195,579 gt Pentium with bug(assuming Excel
  doesnt already have SW bug patch)
• Rarely noticed since error in 5th significant
  digit
• Success of IEEE standard made discovery possible
  all computers should get same answer

54
Pentium Bug Time line

• June 1994 Intel discovers bug in Pentium takes
  months to make change, reverify, put into
  production plans good chips in January 1995 4 to
  5 million Pentiums produced with bug
• Scientist suspects errors and posts on Internet
  in September 1994
• Nov. 22 Intel Press release Can make errors in
  9th digit ... Most engineers and financial
  analysts need only 4 of 5 digits. Theoretical
  mathematician should be concerned. ... So far
  only heard from one.
• Intel claims happens once in 27,000 years for
  typical spread sheet user
• 1000 divides/day x error rate assuming numbers
  random
• Dec 12 IBM claims happens once per 24 days Bans
  Pentium sales
• 5000 divides/second x 15 minutes 4,200,000
  divides/day
• IBM statement http//www.ibm.com/Features/pentium
  .html
• Intel said it regards IBM's decision to halt
  shipments of its Pentium processor-based systems
  as unwarranted.

55
Pentium conclusion Dec. 21, 1994 500M write-off

• To owners of Pentium processor-based computers
  and the PC community
• We at Intel wish to sincerely apologize for our
  handling of the recently
• publicized Pentium processor flaw.
• The Intel Inside symbol means that your
  computer has a microprocessor second to none in
  quality and performance. Thousands of Intel
  employees work very hard to ensure that this is
  true. But no microprocessor is ever perfect.
• What Intel continues to believe is technically
  an extremely minor problem has taken on a life
  of its own. Although Intel firmly stands behind
  the quality of the current version of the Pentium
  processor, we recognize that many users have
  concerns.
• We want to resolve these concerns.
• Intel will exchange the current version of the
  Pentium processor for an
• updated version, in which this floating-point
  divide flaw is corrected, for
• any owner who requests it, free of charge anytime
  during the life of their
• computer. Just call 1-800-628-8686.
• Sincerely,
• Andrew S. Grove Craig R. Barrett
  Gordon E. Moore
• President /CEO Executive Vice
  President Chairman of the Board

56
Summary

• Multiply successive refinement to see final
  design
• 32-bit Adder, 64-bit shift register, 32-bit
  Multiplicand Register
• Booths algorithm to handle signed multiplies
• There are algorithms that calculate many bits of
  multiply per cycle (see exercises 4.36 to 4.39
  in COD)
• Shifter success refinement 1/bit at a time shift
  register to barrel shifter
• Divide can use same hardware as multiply Hi Lo
  registers in MIPS
• Bits have no inherent meaning operations
  determine whether they are really ASCII
  characters, integers, floating point numbers
• Floating point basically follows paper and pencil
  method of scientific notation using integer
  algorithms for multiply and divide of
  significands
• IEEE 754 requires good rounding special values
  for NaN, Infinity

57
To Get More Information

• Chapter 4 of your text book
• David Patterson John Hennessy, Computer
  Organization Design, Morgan Kaufmann
  Publishers, 1994.
• David Winkel Franklin Prosser, The Art of
  Digital Design An Introduction to Top-Down
  Design, Prentice-Hall, Inc., 1980.
• Kai Hwang, Computer Arithmetic Principles,
  architecture, and design, Wiley 1979

58
Acknowledgements

• The majority of slides in this lecture are from
  UC Berkeley for their CS152 course (David
  Patterson, John Kubiatowicz, )