ECE434a Advanced Digital Systems L02

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ECE434aAdvanced Digital SystemsL02

• Electrical and Computer EngineeringUniversity of
  Western Ontario

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Outline

• What we know
• Laws and Theorems of Boolean Algebra
• Simplification of Logic Expressions
• What we do not know
• How to use K-maps for 5, 6 variables
• How to design using only NAND or only NOR gates
• What are tri-state buffers for
• What are basic combinational building blocks
• Multiplexers
• Decoders
• Encoders
• How to implement functions using ROMs, PLAs, and
  PALs

3
Review Laws and Theorems of Boolean Algebra
4
ReviewLaws and Theorems of Boolean Algebra
5
Review Simplifying Logic Expressions

• Combining terms
• Use XYXYX, XXX
• Eliminating terms
• Use XXYX
• Eliminating literals
• Use XXYXY
• Adding redundant terms
• Add 0 XX
• Multiply with 1 (XX)

6
Review Karnaugh Maps

• Example

Sum of products
Product of sums
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Five variable Karnaugh Map

• f(1) 2,3,6,7,9,13,18,19,22,23,24,25,29

BC
BC
00
01
10
11
00
01
11
10
DE
DE







1
00
00
01
01
11
11
10
10
A1
A0
8
Six Variable Karnaugh Map
AB00
AB01
AB10
AB11
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Designing with NAND and NOR Gates (1)

• Implementation of NAND and NOR gates is easier
  than that of AND and OR gates (e.g., CMOS)

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Designing with NAND and NOR Gates (2)

• Any logic function can be realized using only
  NAND or NOR gates gt NAND/NOR is complete
• NAND function is complete can be used to
  generate any logical function
• 1 a I (a a) a a 1
• 0 a I (a a) a I (a a) 1 1 0
• a a a a
• ab (a b) (a b) (a b) ab
• ab (a a) (b b) a b a b

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Conversion to NOR Gates

• Start with POS (Product Of Sums)
• circle 0s in K-maps
• Find network of OR and AND gates

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Conversion to NAND Gates

• Start with SOP (Sum of Products)
• circle 1s in K-maps
• Find network of OR and AND gates

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Tristate Logic and Busses

• Four kinds of tristate buffers
• B is a control input used to enable and disable
  the output

14
Data Transfer Using Tristate Bus
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Combinational-Circuit Building Blocks

• Multiplexers
• Decoders
• Encoders
• Code Converters
• Comparators
• Adders/Subtractors
• Multipliers
• Shifters

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Multiplexers 2-to-1 Multiplexer

• Have number of data inputs, one or more select
  inputs, and one output
• It passes the signal value on one of data inputs
  to the output

w
s
0
w
0
0
f
s
f
w
1
1
w
1
(a) Graphical symbol
(c) Sum-of-products circuit
f
s
w
0
0
w
1
1
(b) Truth table
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Multiplexers 4-to-1 Multiplexer
s
0
s
0
s
f
s
s
1
1
0
w
0
w
00
w
0
0
0
s
0
1
w
01
w
1
0
1
f
1
w
10
w
2
1
0
2
w
w
11
3
w
1
1
1
3
f
(b) Truth table
(a) Graphic symbol
w
2
w
3
(c) Circuit
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Multiplexers Building Larger Mulitplexers
s
0
s
1
s
1
w
s
0
0
w
3
w
0
0
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1
1
w
s
2
4
s
0
3
f
w
1
7
w
f
0
2
w
w
1
3
8
w
11
(a) 4-to-1 using 2-to-1
(b) 16-to-1 using 4-to-1
w
12
w
15
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Synthesis of Logic Functions Using Muxes
w
f
w
w
2
1
2
w
1
0
0
0
0
1
0
1
1
f
1
1
0
1
0
0
1
1
(a) Implementation using a 4-to-1 multiplexer
f
w
w
1
2
f
w
1
w
1
0
0
0
w
0
2
1
0
1
w
w
1
2
2
1
1
0
f
0
1
1
(c) Circuit
(b) Modified truth table
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Synthesis of Logic Functions Using Muxes
w
w
w
f
1
2
3
f
w
w
1
2
0
0
0
0
0
0
0
0
1
0
0
w
0
1
3
1
0
0
0
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1
0
3
w
1
1
1
0
2
1
1
1
w
1
0
0
0
1
0
0
1
1
1
w
1
0
1
1
3
f
1
1
1
1
1
(a) Modified truth table
(b) Circuit
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Decoders n-to-2n Decoder

• Decode encoded information n inputs, 2n outputs
• If En 1, only one output is asserted at a time
• One-hot encoded output
• m-bit binary code where exactly one bit is set to
  1

w
y
0
0
n
n
2
inputs
w
outputs
n
1

y
n
Enable
2
1

En
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Decoders 2-to-4 Decoder
y
w
w
y
y
y
En
0
1
0
1
2
3
w
0
0
0
1
1
0
0
0
y
0
0
1
1
0
1
0
0
w
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
y
x
x
0
0
0
0
0
1
(a) Truth table
y
2
w
y
0
0
w
y
y
1
1
3
y
2
En
y
En
3
(c) Logic circuit
(b) Graphic symbol
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Decoders 3-to-8 Using 2-to-4
w
y
w
y
0
0
0
0
y
w
w
y
1
1
1
1
y
y
2
2
w
2
y
y
En
3
3
y
w
y
En
4
0
0
y
w
y
5
1
1
y
y
2
6
y
y
En
7
3
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Decoders 4-to-16 Using 2-to-4
w
y
w
y
0
0
0
0
y
w
w
y
1
1
1
1
y
y
2
2
y
y
En
3
3
w
y
y
0
0
4
w
y
y
1
1
5
y
y
2
6
w
y
w
y
y
2
En
0
0
3
7
w
y
w
1
1
3
y
2
w
y
y
y
En
En
8
0
0
3
w
y
y
1
1
9
y
y
2
10
y
y
En
3
11
w
y
y
0
0
12
y
w
y
1
1
13
y
y
2
14
y
y
En
3
15
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Encoders

• Opposite of decoders
• Encode given information into a more compact form
• Binary encoders
• 2n inputs into n-bit code
• Exactly one of the input signals should have a
  value of 1,and outputs present the binary number
  that identifies which input is equal to 1
• Use reduce the number of bits (transmitting and
  storing information)

w
0
y
0
n
n
2
outputs
inputs
y
n
1

w
n
2
1

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Encoders 4-to-2 Encoder
w
y
y
w
w
w
3
1
0
2
1
0
w
0
0
0
0
0
0
1
w
1
y
0
1
0
0
1
0
0
1
0
0
1
0
0
w
2
1
1
1
0
0
0
y
1
w
3
(a) Truth table
(b) Circuit
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Encoders Priority Encoders

• Each input has a priority level associated with
  it
• The encoder outputs indicate the active
  inputthat has the highest priority

(a) Truth table for a 4-to-2 priority encoder
w
w
y
y
w
w
z
0
1
0
1
2
3
d
d
0
0
0
0
0
0
0
1
1
0
0
0
x
0
1
1
1
0
0
x
x
1
0
1
1
0
x
x
x
1
1
1
1
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Code Converters

• Convert from one type of input encoding to a
  different output encoding
• E. g., BCD-to-7-segment decoder

w
a
b
w
w
w
c
d
e
f
g
0
1
2
3
a
a
1
1
1
0
0
0
0
1
1
1
0
b
w
0
1
1
1
0
0
0
0
0
0
0
0
b
f
c
w
1
1
0
0
1
0
0
1
1
0
1
1
d
w
1
1
1
1
1
0
0
1
0
0
1
g
2
e
c
e
w
0
1
1
0
0
1
0
0
0
1
1
3
f
1
0
1
0
1
0
1
1
0
1
1
g
d
0
1
1
0
1
0
1
1
1
1
1
(b) 7-segment display
1
1
1
0
1
1
1
0
0
0
0
(a) Code converter
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
(c) Truth table
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Extension of Digital Design Fundamental

• What is the optimization?
• Synthesis
• Design project 1
• Optimization based on majority gate
• Modified K-map based on majority gate
• Optimization based on pass gate
• Modified K-map based on pass gate

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Programmable Logic Devices

• Read Only Memories (ROMs)
• Programmable Logic Arrays (PLAs)
• Programmable Array Logic Devices (PALs)

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Read-Only Memories

• Store binary data
• data can be read out whenever desired
• cannot be changed under normal operating
  conditions
• n input lines, m output lines gt array of 2n
  m-bit words
• Input lines serve as an address to select on of
  2n words
• Use ROM to implement logic functions?
• n variables, m functions

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Basic ROM Structure
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ROM Types

• Mask-programmable ROM
• Data is permanently stored (include or omit the
  switching elements)
• Economically feasible for a large quantity
• EPROM (Erasable Programmable ROM)
• Use special charge-storage mechanism to enable or
  disable the switching elements in the memory
  array
• PROM programmer is used to provide appropriate
  voltage pulses to store electronic charges
• Data is permanent until erased using an
  ultraviolet light
• EEPROM Electrically Erasable PROM
• erasure is accomplished using electrical pulses
  (can be reprogrammed typically 100 to 1000
  times)
• Flash memories - similar to EEPROM except they
  use a different charge-storage mechanism
• usually have built-in programming and erase
  capability, so the data can be written to the
  flash memory while it is in place, without the
  need for a separate programmer

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Programmable Logic Arrays (PLAs)

• Perform the same function as a ROM
• n inputs and m outputs m functions of n
  variables
• AND array realizes product terms of the input
  variables
• OR array ORs together the product terms

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PLA 3 inputs, 5 p.t., 4 outputs
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nMOS NOR Gate
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AND-OR Array Equivalent
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To Do

• Textbook
• Chapter 1.3, 1.4, 1.13
• Read
• Alteras MAXplus II and the UP1 Educational
  boardA Users Guide, B. E. Wells, S. M. Loo
• Altera University Program Design Laboratory
  Package
• Design Project 1 majority gate and pass gate