Quantitative approach to ISA design and compilation for code size reduction

1
Quantitative approach to ISA design and
compilation for code size reduction

• SimpLight Nanoelectronics Ltd
• Kevin Lo, Lin Ma

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Outline

• Introduction
• Problem definition
• Existing approach
• Our approach
• Hardware support
• compiler support
• Experimental Results
• Summary

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Introduction

• Code Size is a critical issue for Embedded
  Applications.
• Mixed size Instruction Set is commonly used
• Normal length instruction set
• Compressed length instruction set

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Problem definition

• Trade off between
• Maximum code size compression ratio.
• Least degradation in performance.
• Implementation cost

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Existing approach
Scheme Methodology Decoding Compression ratio Performance Penalty Hardware Cost Compiler complexity
ARM -Thumb Extended ISA mode Switching Instruction mapping 20-30 Very High Thumb Engine Low
ARM - Thumb-2 Separated ISA with Mapping Engine Instruction mapping 15-25 High Thumb-2 instruction mapping Engine High
MIPS - MIPS16e Extended ISA mode Switching Native support 20-30 Very High Special branch detection engine Low
IBM- CodePack Binary Compression via software engine Build-in de-compressor Engine 20-30 Negligible Hardware de-compressor No effort
ARC- ARCompact 16-bit instruction support via User defined interface Native support 20-40 Negligible Complex reconfigurable processor Low
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Instruction Analysis

• Real applications
• Uclibc Open source c-library package for
  embedded applications
• 729a Voice codec program used in mobile phones
• Mpeg4 MPEG-4/ASP decoder program
• Nucleus RTOS for embedded processors (ported to
  the Mips-like architecture)
• Libmad MPEG audio decoder library
• Uclinux Linux kernel release 2.6.xx for embedded
  processors
• Lay2/3 Layer 2 and Layer 3 of the GSM wireless
  communication protocol stack

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Instruction Analysis
32-bit instruction format
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3 use 16-bit or less
16-bit instruction format
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8 result one operand
16-bit instruction format
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20.9 use 0
16-bit instruction format
2 GPRs imm5
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21.3 use stack pointer
16-bit instruction format
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4.4 use immediate 0
16-bit instruction format
2 GPRs imm5
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Total 47.47 could only use 16-bit
16-bit instruction format
Maximum 24 code size reduction ratio
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Hardware support

• Decoding phase-instruction fetching handler
• For word aligned 16-bit instruction same as
  32-bit
• For half-word aligned 16-bit instruction shift
  to form a word alignment 32-bit

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Compiler support
Normal Instruction Set
Analyze OP to tag candidates Schedule for max
paired 16-bit OPs
Mixed instruction
Assembly
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Scheduling for code size

• Object
• Get more paired 16-bit OPs
• Heuristic for code size purpose
• At step t, data ready instructions in a priority
  list OP16_1t, OP32_2t , OP16_1t is a best
  candidate if satisfies
• OP16_it is the only candidate
• More than One 16-bit instructions in the priority
  list
• At step t-1, an unpaired OP16_jt-1 was issued.
• use original scheduling policy to loop body BB to
  minimize performance degradation

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Experiments result

• Code size compression ratio
• About 17-23

Scheduling policy perf original
size code size to all BBs
perfsize code size to non loop body BBs
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Experiments result

• Performance
• slight improvement to performance from 0.6 to
  4.6

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Summary

• A simple but effective approach to implement code
  size reduction
• Focus on instruction analysis with real
  applications
• Using all registers
• Scheduling policy for code size purpose
• Little cost in hardware
• About 17-23 compression ratio and slight
  improvement to performance from 0.6 to 4.6

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• Thank you !