BTeV Trigger

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BTeV Trigger

• BEAUTY 2003
• 9th International Conference on B-Physics at
  Hadron Machines
• Oct. 14-18, 2003, Carnegie Mellon University
• Michael Wang, Fermilab
• (for the BTeV collaboration)

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BTeV - a hadron collider B-physics experiment
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BTeV detector in the C0 collision hall
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BTeV detector
30 Station Pixel Detector
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Si pixel detector
14,080 pixels (128 rows x 110 cols)
total of 23Million pixels in the full pixel
detector
380,160 pixels per half-station
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Simulated B event
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Simulated B event
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Primary interaction vertex
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Primary interaction vertex
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B decay vertex
K
Bs
Ds
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L1 vertex trigger algorithm

• Two stage trigger algorithm
• Segment finding
• Track/vertex finding

1) Segment finding stage Use pixel hits from
3 neighboring stations to find the beginning
and ending segments of tracks. These segments
are referred to as triplets
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Segment finding inner triplets
1a) Segment finding stage phase 1 Start
with inner triplets close to the interaction
region. An inner triplet represents the
start of a track.
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Segment finding outer triplets
Track/vertex finding
1b) Segment finding stage phase 2 Next,
find the outer triplets close to the boundaries
of the pixel detector volume. An outer
triplet represents the end of a track.
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Track/vertex finding
2a) Track finding phase Finally, match the
inner triplets with the outer triplets to
find complete tracks.

• 2b) Vertex finding phase
• Use reconstructed tracks to locate interaction
  vertices
• Search for tracks detached from interaction
  vertices

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Trigger decision
Execute Trigger
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BTeV trigger overview
L1 rate reduction 100x
L2/3 rate reduction 20x
4 KHz
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Level 1 vertex trigger architecture
30 station pixel detector
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Pixel data readout
time-stamp expansion
time ordering
clustering algorithm
xy table lookup
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L1 segment finder hardware
Is there a hit?
Matching hit?
Matching hit?
Within beam hole?
Matching hit?
Project to non-bend plane N1
Look at non-bend plane N
Project to non-bend plane N
Project to non-bend plane
Look at non-bend plane N1
Start with bend view hits on N-1 and N
Now look at non-bend plane N-1
Project downstream
Project upstream
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L1 segment finder on PTA card
Uses Altera APEX EPC20K1000 instead of EP20K200
on regular PTA
Modified version of PCI Test Adapter card
developed at Fermilab for testing hardware
implementation of 3-station segment finder
(a.k.a. Super PTA)
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L1 track/vertex farm hardware
Block diagram of pre-prototype L1 track/vertex
farm hardware
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L1 trigger pre-prototype board
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L1 pre-prototype with DSP mezzanine cards
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L1 trigger pre-prototype test stand
Hitachi programming
Xilinx programming cable
ArcNet
serial console
PCI test adapter
TI DSP JTAG emulator
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Level 2/3 trigger RD
24-port fanout switch
Processing nodes from retired Fermilab farm
High-density blade server under evaluation
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BTeV trigger architecture
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Real Time Embedded Systems (RTES)

• RTES NSF ITR (Information Technology Research)
  funded project

• Collaboration of computer scientists, physicists
  engineers from
• Univ. of Illinois, Pittsburgh, Syracuse,
  Vanderbilt Fermilab

• Working to address problem of reliability in
  large-scale clusters with real time constraints

• BTeV trigger provides concrete problem for RTES
  on which to conduct their research
• and apply their solutions

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End
End
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Backup slides
Backup slides
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L1 trigger efficiencies
Process Efficiency Efficiency

Minimum bias 1 1
Bs DsK- 80 65 45 74 80 80 65 45 74 80
B0 J/yK s 80 65 45 74 80 80 65 45 74 80
B- Ksp - 80 65 45 74 80 80 65 45 74 80
B- fKs 80 65 45 74 80 80 65 45 74 80
B0 2-body modes 80 65 45 74 80 80 65 45 74 80
(pp-,Kp-,KK-) 80 65 45 74 80 80 65 45 74 80
L1 vertex trigger efficiencies
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L2 trigger efficiencies
Process Efficiency Efficiency

Light quark 7 7
Bs DsK- 85 78 72 87 85 78 72 87
B0 J/yK s 85 78 72 87 85 78 72 87
B- Ksp - 85 78 72 87 85 78 72 87
B- p p - 85 78 72 87 85 78 72 87
L2/L1 trigger efficiencies