AVR Startup and Memories

1
AVR Startup and Memories

• Assembly Language Programming
• University of Akron
• Dr. Tim Margush

2
The Boot

• Switch on!
• Now what?

• What's in the program counter?
• What's in memory?
• AVR Reset Interrupt

3
RESET

• Five sources
• Power on
• External
• Watchdog
• Brown-out
• JTAG

• Reset actions
• I/O Registers set to default states
• PC 0, causing execution of RESET vector
• A delay allows power levels to stabilize before
  execution begins

4
Interrupts

• Interrupt the normal flow of execution
• Occurs between two instructions
• After execute, before fetch
• Similar to a call/return, but there is no
  explicit call instruction
• Triggered by a hardware signal or condition
  caused by software
• Stack must be initialized before interrupts occur

5
Interrupt Numbering

• Interrupts are numbered by priority
• 0, 1, 2, lower prioritygtgtgt
• Each interrupt is associated with a program
  memory address
• 0-gt0, 1-gt2, 2-gt4, etc
• This address should hold a vector to the
  interrupt service routine
• JMP isr

6
Interrupt Service Routine

• A procedure that handles the interrupt
• This can be anywhere in program memory
• It should exit via the RETI instruction
• ISRs must not change status flags
• Interrupts are disabled until a program enables
  them
• SEI (Set Interrupt Enable flag)

7
AVR Memories

• SRAM
• Volatile storage for working variables not held
  in registers
• Flash
• Holds instructions and constant data
• Special instruction allows a byte of program
  memory to be loaded into a register
• EEPROM
• Secondary storage accessed via I/O registers

8
SRAM

• The AVR data address space is addressed linearly
• Addresses 00 - 1F correspond to the 32 general
  purpose registers
• Addresses 20 - 5F correspond to the 64 I/O
  registers
• Addresses 60 - 45F are SRAM locations

9
SRAM Organization

• Applications usually divide SRAM into three areas
• static storage
• 60 to HEAP_START
• heap storage
• HEAP_START to HEAP_END
• stack space
• HEAP_END to 45F

10
Reading and Writing Data

• There are several ways to specify an address when
  accessing the data space
• direct addressing, indirect addressing, and
  indirect with displacement, pre-decrement, or
  post-increment
• Bytes are read from the data space into a
  register using a load command
• Bytes are written from a register to the data
  space using a store command

11
Load Direct

• LDS Rd, k LoaD direct from data Space
• Rd is any register
• k is any 16-bit address
• The largest address in the ATMega16 is 045F, so
  only 11 bits are really needed
• This is a 32-bit instruction and requires 2 clock
  cycles
• The first word specifies the instruction and
  destination register
• The second word contains the address

12
Store Direct

• STS k, Rr STore direct to data Space
• Rr is any register
• k is any 16-bit address
• The largest address in the ATMega16 is 045F, so
  only 11 bits are really needed
• This is a 32-bit instruction and requires 2 clock
  cycles
• The first word specifies the instruction and
  source register
• The second word contains the address

13
Static Variables

• Static data is allocated in SRAM.
• Initialization must be done during execution.
• char a1, b
• b a 1

• .dseg
• a .byte 1 allocation
• b .byte 1
• .cseg
• ldi r16, 1 initialize
• sts a, r16
• lds r16, a assign
• inc r16
• sts b, r16

14
Static Variables

• Multi-byte data is handled similarly
• int a-3657
• int b
• a a - b

• .dseg
• a .byte 2
• b .byte 2
• .cseg
• initialization code
• ldi r16, low(-3657)
• sts a, r16
• ldi r16, high(-3657)
• sts a1, r16

15
Static Variables

• int a-3657
• int b
• The assignment requires the two step subtraction
  sequence
• a a - b

• lds r6,a r7r6 a
• lds r7,a1
• lds r8,b r9r8 b
• lds r9,b1
• sub r6,r8 r7r6 a-b
• subc r7,r9
• sts a,r6 a r7r6
• sts a1,r7

16
Timing

• The load and store instructions can be used to
  access general purpose or I/O registers
• Because they are 32-bit instructions and require
  2 clock cycles, this option should only be used
  for special purposes
• MOV copies data between registers in 1 clock
  cycle and is a 16-bit instruction
• IN and OUT copy data between I/O and general
  registers in a single clock cycle and are 16 bit
  instructions

17
Indirect Addressing

• Memory access requires an address
• Direct addressing means the address is coded
  directly in the instruction
• LDS R0,013C is encoded as 9000013C
• Indirect addressing means the address is stored
  elsewhere The instruction includes information
  telling where the actual address can be found
• LD R0, X is encoded as 900C
• C indicates register X (R27R26) will act as a
  pointer to memory

18
Load and Store Indirect

• Indirect addressing mode can use registers X, Y,
  or Z as the pointer
• LD Rd, Z
• LoaD indirect
• ST Y, Rr
• STore indirect
• Indirect access requires 2 clock cycles

19
Indirect with Displacement

• This is like indirect addressing, except that a
  calculation is involved
• A displacement (constant) is added to the
  indirect address to determine the effective
  address
• The displacement is coded in the instruction
• LDD R0, Y4 is coded 800C (1000000000001100)
• The binary code for the displacement is scattered
  among several bits of the instruction so can not
  be easily seen
• The effective address in this case is 4 bytes
  past the location pointed to by Y

20
Load and Store with Displacement

• Indirect with displacement is available only with
  Y and Z
• LDD Rd, Yq
• LoaD indirect with Displacement
• STD Zq, Rr
• STore indirect with Displacement
• The displacement q is limited to 0-63
• The displacement is unsigned (positive)

21
Indirect with Post-Increment

• Typically used in a looping structure to
  sequentially access memory by increasing
  addresses
• Set Y to first byte
• Access repeatedly using post-increment to point
  to the next byte after each access
• LD Rd, Y

22
Load and Store Post-Increment

• Post increment is available with X, Y, or Z
• LD Rd, X
• Load indirect with post-increment
• ST Z,Rr
• Store indirect with post-increment
• Do not use the same registers for pointers and
  data as such operations are undefined

23
Indirect with Pre-Decrement

• Typically used in a looping structure to
  sequentially access memory by decreasing
  addresses
• Set Y to 1 address of last first byte
• Access repeatedly using pre-decrement to point to
  the byte accessed
• LD Rd, -Y

24
Load and Store Pre-Decrement

• Pre decrement is available with X, Y, or Z
• LD Rd, -X
• Load indirect with pre-decrement
• ST -Z,Rr
• Store indirect with pre-decrement
• Do not use the same registers for pointers and
  data as such operations are undefined

25
Applications of Indirect Addressing

• Array access
• array base address calculated offset
• offset will be index size of each element
• char b, a30
• b ai

• a .byte 30 array
• b .byte 1
• ldi xh, high(a)
• ldi xl, low(a)
• lds r16, i
• add xl, r16
• brcc PC2
• inc xh
• ld r16, X
• sts b, r16

Indirect addressing to access ai
26
Applications of Indirect Addressing

• Pointers or references
• ptr holds the address of a variable
• int a
• int ptr a
• (ptr)

• a .byte 2
• ptr .byte 2
• ldi r16, low(a)
• sts ptr, r16
• ldi r16, high(a)
• sts ptr1, r16
• lds zl, ptr
• lds zh, ptr1
• ld r24, Z
• ld r25, Z1
• adiw r25r24, 1
• st Z, r24
• st Z1, r25

Pointer accesses the integer variable a
27
Stack

• The stack is an area of SRAM that grows downward
  from a fixed reference point
• Special instructions and I/O register support
  stack access
• RET, CALL, PUSH, POP,
• SP (Stack Pointer)
• The stack requires initialization
• Set SP to an appropriate address (empty stack)
• The stack is managed by application and processor
  interrupt system

28
Stack Initialization

• Typically, the stack starts at the highest SRAM
  address and grows downward through memory
• SP points to the next available byte of stack
  storage (top of stack after a push)
• ldi R16, high(RAMEND)
• out SPH, R16
• ldi R16, low(RAMEND)
• out SPL, R16

29
PUSH and POP

• push Rr
• Register data copied to byte at address in SP
• SP is decremented

• pop Rd
• SP is incremented
• Byte at address in SP is copied to Rd

30
Stack Usage

• Temporary storage of information
• Storage for local variables during execution of a
  procedure
• Storage of return addresses for procedure and
  interrupt calls

31
Flash

• Instructions are fetched using a dedicated
  address and data bus
• PC is the address
• Fetched word is loaded into the instruction queue
• This is part of the natural fetch-execute cycle

32
PC

• The program counter indicates an address (word
  address) in flash
• Processor RESET sets PC to 0
• Each fetch increments PC by 1 or 2
• Branching instructions may load PC with new
  address

33
Data in Flash

• Accessed via special instruction
• LPM Rd, Z load register from program memory
• The address of the byte to be read must be preset
  in register Z (R31R30)
• Z is a byte address
• Z/2 is the word address and the entire word is
  read from flash
• Z2 selects the low or high byte from the word
  and that yte is placed in Rd
• Z0 0 selects the low byte
• Z0 1 selects the high byte

34
Example

• .cseg
• age .dw 1000 word value 03E8 (E8, 03)
• Read age into R7R6
• ldi zh, high(age2) convert to byte address
• ldi zl, low(age2)
• lpm R6, Z Z points to byte containing E8
• adiw zHzL, 1 point to next byte
• lpm R7, Z Z points to byte containing 03
• R7R6 now contains 03E8

35
LPM Variations

• LPM (not recommended)
• Assumes Rd is R0 and Z contains the address
• LPM Rd, Z
• Allows any register for the destination
• LPM Rd, Z
• Increments Z after the load
• This can be used to access a sequence of bytes
• Avoid using R30 or R31 as Rd

36
SPM

• Store Program Memory is used to write a new
  program (or data) into flash
• It requires an erase of an entire page (64 words)
  before writes may occur
• Some devices require whole pages to be written at
  one time
• It may only be executed from a special area of
  flash called the Boot Loader Section (BLS)

37
EEPROM

• EEPROM 512 byte storage is accessed via I/O
  registers
• The address to be accessed is placed in the EE
  Address Register
• EEARHEEARL
• 512 bytes requires a 9-bit address
• Only bit 0 of EEARH is used

.equ addr 74prepare to accessEEPROM byte
at addrldi R17, high(addr)ldi R16,
low(addr)out EEARH, R17out EEARL, R16
38
EEPROM

• Data is transferred between the EEPROM storage
  and the EE Data Register
• EEDR
• Data to be written or data just read
• A read operation copies a byte from EEPROM to
  EEDR
• A Write operation copies EEDR to the specified
  byte of EEPROM

39
EEPROM

• The EEPROM control register EECR controls the
  actions of the memory
• Bit 0 EERE Read Enable
• Bit 1 EEWE Write Enable
• Bit 2 EEMWE Master Write Enable
• Bit 3 EERIE Ready Interrupt Enable

40
Reading from EEPROM
.equ addr 74prepare to accessEEPROM byte
at addrldi R17, high(addr)ldi R16,
low(addr)out EEARH, R17out EEARL, R16trigger
readsbi EECR, EEREaccess datain R16, EEDR

• Setup the address
• Issue a read signal
• Write a 1 to EERE bit
• Access the data
• Data appears in EEDR
• The processor stops for 4 clock cycles when a
  read is requested

41
Writing to EEPROM
.equ addr 74.def data R18prepare to
writedata to EEPROMldi R17, high(addr)ldi
R16, low(addr)out EEARH, R17out EEARL, R16out
EEDR, dataenable master writesbi EECR,
EEMWEenable writesbi EECR, EEWEwrite cycle
started

• Setup the address
• Put data in EEDR
• Set EEMWE
• Set EEWE
• Within 4 cycles or EEMWE bit is automatically
  reset to prevent unintentional writes
• Processor halts for 2 clock cycles
• Wait before writing more data
• EEWE will reset when previous write is complete
• This requires about 8.5 ms (milliseconds!)