Current Testable Design of Resistor String DACs

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Current Testable Design of Resistor String DACs

• Proceedings of the third IEEE international
  workshop on electronic design, Test and
  Applications , 2005
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• ?? 95662009

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outline

• 1. Introduction
• 2. Supply current tests of resistor
• string DACs
• 3. DFT of DACs for current testing
• 4. Conclusion

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Introduction

• In this paper, supply current testability is
  examined experimentally for opens and shorts in a
  general 3 bit resistor string Digital/Analog
  converter(DAC).
• we attempted to examine testability of shorts and
  opens in a DAC in order to check the feasibility
  of DAC testing based on supply current
• we show testability analysis results of current
  testing in a conventional resistor string DAC.
  Also, we propose a DFT method of such DACs for
  supply current testing.

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Supply current tests of resistor string DACs

• A resistor string DAC is made of a resistor
  string and MOS switches. Besides them, an
  operational amplifier and inverter gates are
  added to the DAC.
• In our experiments, a short is inserted between
  targeted terminals by adding a resistor of 0.1O
  between them in the Spice file of the defect-free
  circuit. An open is inserted to a targeted
  terminal by adding a resistor of 10GO to the
  SPICE file.

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3 bit resistor string DAC
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DFT of DACs for current testing

• shorts in DACs will be detected, but opens in MOS
  switches will not be detected by the current
  testing
• In our design, a transfer gate, an inverter gate
  and a resistor, Rp, are added to the conventional
  DAC. In the normal mode, Tst is H. In the test
  mode, Tst is L and current through Rp is
  measured.

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Our proposed DAC
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Conclusion

• In order to detect them by current testing, we
  have proposed a DFT method for register string
  DACs. It is shown experimentally that all of the
  opens and shorts will be detected in resistor
  string DACs designed by using the DFT method.
• Exhausted test vector application is required in
  tests of the testable designed DAC. It leads to
  long test time and some restriction in
  application of the DFT method.

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Layout of our testable DAC
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• Defect coverage of DAC
• Defect coverage of our testable DAC