Chidamber Kulkarni, Gordon Brebner, Graham Schelle

1
Mapping a Domain Specific Language to a Platform
FPGA

• Chidamber Kulkarni, Gordon Brebner, Graham
  Schelle
• Xilinx Inc
• University of Colorado, Boulder

2
Outline

• Motivation
• Introduction to Click
• Related Work
• Cliff Click for FPGAs
• Initial results
• Summary

3
Why Programmable Logic?

• Fewer ASIC design starts
• higher development costs
• manufacturing risks
• time-to-market pressures
• Programmable logic solutions potentially provide
• cheaper development costs
• predictable design flow
• shorter design time
• Shift to PLDs is already happening in many
  domains
• cellular telephony, digital audio/video,
  printers, SDR

4
Some Observations on Programmability of PLDs

• PLDs employ numerous architectural featuresto
  enable high performance implementation (spatial
  concurrency, specialized operators, distributed
  many port memories, serial transceivers, ...)
• (however) Ease of programmabilityremains elusive
• PLDs are essentially under-utilized

5
Why Use a Domain Specific Language

• Higher initial cost for using a DSL, but total
  design cost is less
• Ease of managing the code, reusability, and
  readability (higher productivity)
• Examples
• Matlab for DSP applications
• OpenGL for graphics

Total Design Time
Design Cost
HDL
T0
Domain Specific Language
T1
C1
Start up Cost
C0
Design life cycle
Reduction in design time
Based on Hudaks model
6
Outline

• Motivation
• Introduction to Click
• Related Work
• Cliff Click for FPGAs
• Initial results
• Summary

7
Click Overview I

• Eddie Kohler, et al (MIT)
• Software Modular Router
• Graph based packet handling
• Creating router as simpleas hooking togetherthe
  elements

8
Click Overview II

• Written in C
• Allows inheritance of common interface(Element
  class)
• Push send packet downstream
• Pull polling of packets from upstream
• Complex constructors for elements
• Complex data structures
• Dynamic data structures

9
Click Overview III

• Strengths
• modularity
• library of reusable elements
• open source
• Weaknesses
• sequential processing
• overhead that comes with reusability

10
Outline

• Motivation
• Problem Statement
• Related Work
• Cliff Click for FPGAs
• Initial results
• Summary

11
Related Work

• Many goals
• real-time performance, ease of use, formal
  aspects, modeling/simulation, support for
  heterogeneous elements
• Common approaches
• Library-based approach Hwang et al, FPL01
• Compilation-based approach Haldar et al, DAC01
• Soft platforms Brebner et al, ASAP04

12
Outline

• Motivation
• Introduction to Click
• Related Work
• Cliff Click for FPGAs
• Evaluation
• Summary

13
What is Cliff?

• Embedding Click in Verilog for mappingonto FPGAs
• Keep sequential nature at first
• optimization left for future work
• Keep reusable element structure
• Inter-element communication
• memory interfaces
• Cliff Diver
• Click Graph gt Verilog Top-level Glue

14
Cliff Packet Passing

• Same flow as Click
• Pass packet header only payload offloaded
• Header travels through elements
• classification/scheduler
• error checking
• routing
• sent to Ethernet MAC

15
Cliff Elements
Memory interface
Enable, addr, data

• Verilog
• FSM with 2 predefined states
• Replaces Click push/pull
• User defined states
• Packet handling
• Control hardware
• Can access memory

data
Rdy_send_in1
Rdy_send_in0
Rdy_recv_out0
Rdy_recv_out1
Inter-element communication
16
Cliff Element Graph

• Can connect elementsjust like in Click
• Common interface allowstrivial
  connectionsbetween arbitrary elements
• A script (CliffDiver)is used to
  createconnections

17
Outline

• Motivation
• Problem Statement
• Related Work
• Cliff Click for FPGAs
• Initial results
• Summary

18
Cliff Design Flow
Click Design
C
Pre-defined Click elements (in Verilog)
Cliff Diver
Verilog
Standard FPGA Backend Tools
Simulation Synthesis Place Route
Bit stream
19
Initial Results

• 3 Click benchmarks
• Excluding area needed forfour GMAC cores(1200
  slices for each)
• Used ISE 5.2 tools MemOrg1has a 344-bit wide
  registered datapath for headers,and BRAM
  forpayload storage
• MemOrg2 has four singleported BRAMs connectedto
  all Cliff element - packets stored
  alternatelyover BRAMs

20
Outline

• Motivation
• Problem Statement
• Related Work
• Cliff Click for FPGAs
• Initial results
• Summary

21
Summary

• Ease of programmability a significant barrier
  todeploying FPGAs
• closing the gap with ASIPs/multiprocessors
• Cliff a direct implementation of Click
  semanticsin Verilog
• demonstrates a library based mapping
• implemented many click elements
• synthesized a two port IPv4 router, a simple NAT,
  and DiffServ
• estimated performance meets the required
  throughput
• Push Cliff to universities by end 2004